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Part: 5102ALP
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
Description: A/DConverter, 16-bit, 20kHz, Latch- Protected
Company: Maxwell Technologies
Datasheet: Download 5102ALP datasheet File size : 147 kB
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Datasheet text preview:
SPACE ELECTRONICS INC.
S PA CE PRODUCTS
16-B IT, 20 KHZ A/D CONVERTER
5102ALPRP
44
+VDIG DGND -VDIG -VDIG RST CLKIN XOUT STBY DGND +VDIG TRK1 TRK2 CRS/FIN SSH/SDL HOLD CH1/2 SCLK +LPTBIT NC -VDIG DGND +VDIG
1
+VANLOG AGND -VANLOG SLEEP SCKMOD LPTSTATUS +VANLOG AIN2 -VANLOG AGND REFBUF VREF AIN1 OUTMOD BP/UP CODE SDATA +LPTV -LPTV -VANLOG AGND
VA+ VADGND VDVD+ AGND AIN2 CH1/2 AIN1 VREF + CLKIN XOUT REFBUF SLEEP HOLD RST STBY CODE BP/UP CRS/FIN TRK1 TRK2 SSH/SDL SDATA
Clock Generator
Control Calibration SRAM
SCLK
Microcontroller
TEST
+
16-Bit charge Redistribution DAC
SCKMOD + Comparator OUTMOD
+
Memory
22
23
+VAN
FEAT URES :
· Monolithic CMOS A/D converters - Inherent sampling architecture - 2-channel input multiplexer - Flexible serial output port · Conversion time - 5102A: 40 µs · Linearity error: ±0.001% FS - Guaranteed no missing codes · Self-calibration maintains accuracy - Over time and temperature · Fully latchup protected
DE SC RIPTION:
Space Electronics' 5102ALPRP is a 16-bit monolithic CMOS analog-todigital converter capable of 20 kHz throughput. On-chip self-calibration achieves nonlinearity of ±0.001% of FS and guarantees 16-bit no missing codes over the entire specified temperature range. Offset and fullscale errors are minimized during the calibration cycle, eliminating the need for external trimming. The 5102ALPRP each consist of a 2-channel input multiplexer, DAC, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. The inherent sampling architecture of the device eliminates the need for an external track and hold amplifier. The converters' 16-bit data is output in serial form with either binary or 2's complement coding. Three output timing modes are available for easy interfacing to microcontrollers and shift registers. Unipolar and bipolar input ranges and digitally selectable.
0627.00Rev2
All data sheets are subject to change without notice
1
(858) 452-4167 - Fax: (858) 452-5499 - www.spaceelectronics.com
©2000 Space Electronics Inc. All rights reserved.
5102ALPRP
16-B IT, 20 KHZ A/D CONVERTER
TABLE 1. 5102ALPRP ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0V, ALL VOLTAGES WIT H RESPE CT TO GROUND)
PAR AME TE R DC Power Supplies: 1 Positive Digital Negative Digital Positive Analog Negative Analog Input Current, Any Pin Except Supplies 2 Analog Input Voltage (AIN and VREF pins) Digital Input Voltage Ambient Operating Temperature Storage Temperature 1. In addition, VD+ must not be greater than (VA+) 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latchup.
SYMBO L VD+ VDVA+ VAIIN V INA V IND TA TSTG
MI N -0.3 0.3 -0.3 0.3 -(VA-) -0.3 -0.3 -15 -65
MAX 6.0 -6.0 6.0 -6.0 ±10 (VA+) 0.3 (VA+) 0.3 55 150
U NIT V
mA V V
oC oC
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TABLE 2. 5102ALPRP RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0V, ALL VOLTAGES WIT H RESPE CT TO GROUND) PAR AME TE R DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog Analog Reference Voltage Analog Input Voltage 1 Unipolar Bipolar SYMBO L VD+ VDVA+ VAVREF VAIN AGND -V REF --V REF V REF MI N 4.5 -4.5 4.5 -4.5 2.5 TYP 5.0 -5.0 5.0 -5.0 4.5 MAX VA+ -5.5 5.5 -5.5 (VA+) -0.5 V V U NIT V
1. The 5102ALPRP can accept input voltage up to the analog supplies (VA+ and VA-). They will produce an output of all 1s for inputs above VREF and all 0s for inputs below AGND in unipolar mode and -VREF in bipolar mode, with binary coding (CODE = low).
0627.00Rev2
All data sheets are subject to change without notice
2
©2000 Space Electronics Inc. All rights reserved.
5102ALPRP
16-B IT, 20 KHZ A/D CONVERTER
TABL E 3. ANALOG CHARACTERISTICS (TA = TMIN TO T MAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; FULL-SCALE INPUT SINEWAVE, 200 HZ; CLKIN = 1.6 MHZ; fS = 20 KHZ; BIPOLAR MODE; FRN MODE; AIN1 AND AIN2 TIED TOGETHER, EACH CHANNE L TESTED SEPARATELY; ANALOG SOURCE IMPEDANCE = 50 WITH 1000 PF TO AGND UNLESS OT HERWI SE SPECIFIED)
PAR AME TE R Accuracy Resolution 1 Full Scale Error 2 Drift 3 Unipolar Offset 2 Drift 3 Bipolar Offset 2 Drift 3 Bipolar Negative Full Scale Error 2 Drift 2 Integral Nonlinearity Differential Nonlinearity Dynamic Performance (Bipolar Mode) Peak Harmonic or Spurious Noise 2, 4 Total Harmonic Distortion 4 Signal-to-Noise Ratio 2, 4 0 dB Input -60 dB Input Noise 5 Unipolar Mode Bipolar Mode Analog Input Aperture Time Aperture Jitter Input Capacitance 6, 4 Unipolar Mode Bipolar Mode Conversion and Throughput Conversion Time 7 Acquisition Time 8 Throughput 9, 10 Power Supplies Power Supply Current 11 Positive Analog Negative Analog (SLEEP High) Positive Digital Negative Digital mA IA+ I AID+ I D----8.5 -7.7 0.5 -0.5 12 -11 1.5 -1.5 tc ta ftp ---40.625 9.375 20 ---µs µs kHz --335 215 ----30 100 --ns ps pF 94 -87 ---100 0.002 90 30 35 70 ----µVrms --dB % dB RES FSE VOFF BOFF BNFSE INL DNL 16 -----------±1 ±2 ±1 ±2 ±2 ±2 ±2 ±2 -±1 -±5 -±5 -±5 -±5 -±3 -Bits LSB L S B LSB L S B LSB L S B LSB L S B LSB LSB SYMBO L MI N TYP MAX U NIT
Memory
0627.00Rev2
All data sheets are subject to change without notice
3
©2000 Space Electronics Inc. All rights reserved.
5102ALPRP
16-B IT, 20 KHZ A/D CONVERTER
TABL E 3. ANALOG CHARACTERISTICS (TA = TMIN TO T MAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; FULL-SCALE INPUT SINEWAVE, 200 HZ; CLKIN = 1.6 MHZ; fS = 20 KHZ; BIPOLAR MODE; FRN MODE; AIN1 AND AIN2 TIED TOGETHER, EACH CHANNE L TESTED SEPARATELY; ANALOG SOURCE IMPEDANCE = 50 WITH 1000 PF TO AGND UNLESS OT HERWI SE SPECIFIED)
PAR AME TE R Power Consumption 11, 12 (SLEEP High) (SLEEP Low) Power Supply Rejection 13 Positive Supplies Negative Supplies SYMBO L Pdo P ds PSR PSR MI N ----TYP 85 45 84 84 MAX 130 -dB --U NIT mW
1. Minimum resolution for which no missing codes are guaranteed over the specified temperature range. 2. Applies after calibration at any temperature within the specified temperature range. 3. Total drift over specified temperature range after calibration at power-up at 25°C. 4. Guaranteed by characterization (5102A die). 5. Wideband noise aliased into the baseband. Referred to the input. 6. Applied only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF. 7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronrous delay between the falling edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns. 8. The 5102ALPRP requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge. FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 µs with a 1.6 MHz clock; however, in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles. 9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times described above. 10. Typical value (measured). 11. All outputs unloaded. All inputs at VD+ or DGND. 12. Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low). 13. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB.
Memory
TABL E 4. 5102ALPRP SWITCHING CHARACTERISTICS (TA = TMIN TO T MAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; INPUTS: LOGIC 0 = 0V, LOGIC 1 = VD+; CL = 50 PF)
PAR AME TE R CLKIN Period 1, 2 CLKIN Low Time CLKIN High Time Crystal Frequency 1, 2 SLEEP Rising to Oscillator Stable 3 RST Pulse Width 4 RST to STBY Falling RST Rising to STBY Rising CH1/2 Edge to TRK1, TRK2 Rising 5 CH1/2 Edge to TRK1, TRK2 Falling 5
0627.00Rev2
SYMBO L tc l k tclkl tclkh fxtal trst t drrs tc a l tdrsh1 tdfsh4
MI N 0.5 200 200 --150 -----
TYP ---1.6 20 -100 2,882,040 80 --
MAX 10 --------68tclk + 260
U NIT µs ns ns MHz ms ns ns tclk ns ns
All data sheets are subject to change without notice
4
©2000 Space Electronics Inc. All rights reserved.
5102ALPRP
PAR AME TE R HOLD to SSH Falling 6 HOLD to TRK1, TRK2, Falling 6 HOLD to TRK1, TRK2, SSH Rising 6 HOLD Pulse Width 7 HOLD to CH1/2 Edge 6 HOLD Falling to CLKIN Falling 7 PDT and RBT Modes SCLK Input Pulse Period SCLK Input Pulse Width Low SCLK Input Pulse Width High SCLK Input Falling to SDATA Valid HOLD Falling to SDATA Valid - PDT Mode TRK1, TRK2 Falling to SDATA Valid 9 FRN and SSC Modes SCLK Output Pulse Width Low SCLK Output Pulse Width High SDATA Valid Before Rising SCLK SDATA Valid After Rising SCLK SDL Falling to 1st Rising SCLK Last Rising SCLK to SDL Rising HOLD Falling to 1st Falling SCLK CH1/2 Edge to 1st Falling SCLK 1. Minimum CLKIN period is 0.625 µs is FRN mode (20 kHz sample rate). tslkl tslkh t ss tsh trsclk tr s d l thfs tchfs --2tclk - 100 2tclk - 100 --6 t clk -tsclk ts c k l l ts c l k h tdss td h s t dts 500 8 200 8 200 8 ---SYMBO L tdfsh2 tdfsh1 td r s h thold t dhlri t hcf MI N -66tclk -1tclk + 20 300 275
16-B IT, 20 KHZ A/D CONVERTER
TABL E 4. 5102ALPRP SWITCHING CHARACTERISTICS (TA = TMIN TO T MAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; INPUTS: LOGIC 0 = 0V, LOGIC 1 = VD+; CL = 50 PF)
TYP 60 -120 ------100 140 65 2 t clk 2 t clk --2 t clk 2 t clk -7 t clk MAX -68tclk + 260 -63tclk 64tclk 1tclk + 10 ---150 230 125 -----2tclk + 200 8tclk + 200 -U NIT ns ns ns ns ns ns ns ns ns ns ns ns tc l k tc l k ns ns ns ns ns tc l k
Memory
2. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in FRN mode (20 kHz sample rate). 3. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 M parallel resistor. 4. Guaranteed by initial characterization (5102A die). 5. These times are for FRN mode. 6. These times are for PDT and RBT modes. 7. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. 8. Sample tested at 25 o C. Go - No Go. 9. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid t dss time after the next falling SCLK.
0627.00Rev2
All data sheets are subject to change without notice
5
©2000 Space Electronics Inc. All rights reserved.
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