|
|
Part: 9240LPRPQE
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
Description: 14-bit, 10 MSPS Monolithic A/D Converter With LPT Asic
Company: Maxwell Technologies
Datasheet: Download 9240LPRPQE datasheet File size : 2307 kB
Request For quote: Find where to buy 9240LPRPQE
Datasheet text preview:
9240LP
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
AVSS NC SENSE Vref REFCOM NC AVDD BIT 2 BIT 1 OTC NC BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13
NC BIAS CAPB CAPT NC CM L LPTref VinA VinB LPTDVDD LPTAVDD
9240LP
.
DVSS AVSS DVDD AVDD NC DRVDD CL K LPTSTATUS LPTBIT NC BIT 14
Memory
FEATURES:
· RAD-PAK® radiation-hardened against natural space radiation · Low power dissipation: 285 mW · Single 5 V supply · Integral nonlinearity error: 2.5 LSB · Differential nonlinearity error: 0.6 LSB · Input referred noise: 0.36 LSB · Complete: On-chip sample-and-hold amplifier and voltage reference · Signal-to-noise and distortion ratio: 77.5 dB · Spurious-free dynamic range: 90 dB · Out-of-range indicator · Straight binary output data · Total dose hardened to 100 Krads (Si), dependent on orbit and mission duration · Single Event Latchup (SEL) protected
DESCRIPTION:
Maxwell Technologies' 9240LP is a 14-bit, analog-to-digital converter that operates at a 10 MSPS rate. Manufactured with a high speed CMOS process, this ADC contains an on-chip, high performance, low noise, sample-and-hold amplifier and programmable voltage reference. The 9240LP offers single supply operation and dissipates only 480 mW with a 5 volt supply. This device provides no missing codes and excellent temperature drift performance over the full operating temperature range. The 9240LP utilizes Maxwell's LPTTM Latchup Protection Circuit. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides protection to 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class K.
06.13.02 Rev 5 (858) 503-3300- Fax: (858) 503-3301- www.maxwell.com
All data sheets are subject to change without notice
1
©2002 Maxwell Technologies All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
TABLE 1. 9240LP PIN DESCRIPTION
PIN NUMBER 1 2, 29 3 4, 28 5 6 7 8 9 NAME DVSS AVSS DVDD AVDD NC DRVDD CLK LPTSTATUS LPTBIT DESCRIPTION Digital Ground Analog Ground 5V Digital Supply 5V Analog Supply No Connect Digital Output Driver Supply Clock Input Pin A 0 to 5V pulse is output during the decision time and protect time. Normally low. The LPT circuit will crowbar the power supplies to the 9240LP for as long as a logic high is applied. Used to verify operation of the LPT. Normally a logical low or ground is applied to this input. No Connect Least Significant Data Bit (LSB) Data Output Bits Most Significant Data Bits (MSB) Out of Range No Connect Reference Select Reference I/O Reference Common No Connect Power/Speed Programming Noise Reduction Pin Noise Reduction Pin Common-Mod Level (Midsupply) Protected Reference I/O Analog Input Pin (+) Analog Input Pin (-) Protected 5V Digital Supply Protected 5V Analog Supply
9240LP
Memory
10 11 12-23 24 25 26, 27, 30 31 32 33 34, 38 35 36 37 39 40 41 42 43 44
NC BIT 14 BIT 13-BIT 2 BIT 1 OTR NC SENSE V R EF REFCOM NC BIAS 1 CAPB CAPT C ML LPTVREF VINA VINB LPTDVDD LPTAVDD
1. See Speed/Power programmability section.
06.13.02 Rev 5
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
TABLE 2. 9240LP ABSOLUTE MAXIMUM RATINGS 1
PARAMETER +5 V Analog Supply +5 V Digital Supply Analog Ground +5 V Analog Supply Digital Output Driver Supply Digital Output Driver Ground Reference Common Clock Input Pin Digital Outputs Analog Inputs Reference I/O Reference Select Noise Reduction Pins Power/Speed Programming Junction Temperature Operating Temperature Storage Temperature Lead Temperature (10 sec) SYMBOL AVDD DVDD AVSS AVDD DRVDD DRVSS REFCOM C LK Data Out Bits VINA, VINB VREF S ense CAPB, CAPT BIAS TJ TA TSTG TL WITH RESPECT TO AVSS DVSS DVSS DVDD DRVSS AVSS AVSS AVSS DRVSS AVSS AVSS AVSS AVSS AVSS MI N - 0.3 -0.3 -0.3 - 6.5 - 0.3 -0.3 - 0.3 -0.3 - 0.3 - 0 .3 - 0 .3 - 0.3 -0.3 -0.3 --55 -65 -MAX 6.5 6.5 0.3 6.5 6.5 0.3 0.3 AVDD
9240LP
UNIT V V V V V V V V V V V
DRVDD + 0.3 AVDD AVDD AVDD AVDD AVDD + 0.6 150 125 150 300
Memory
V V V
°C
°C
°C °C
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
TABLE 3. DELTA LIMITS
PARAMETER ICC VARIATION ± 10% OF SPECIFIED VALUE IN TABLE 4
06.13.02 Rev 5
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
9240LP
TABLE 4. 9240LP DC SPECIFICATIONS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2 K, VREF = 2.5V,VINA = VINB =± 2.5V DIFFERENTIAL INPUT CENTERED ON VREF(1.25V TO 3.75V ABSOLUTE), TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED)
PARAMETER RESOLUTION MAX CONVERSION RATE MAX REFERRED NOISE1 VREF = 1 V VREF = 2.5V ACCURACY2 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL 3 DNL 3 No Missing Codes Zero Error (@ 25 °C) Gain Error (@ 25 °C) 4,1 Gain Error (@ 25 °C) 5 TEMPERATURE DRIFT Zero Error Gain Error 4 Gain Error 5 POWER SUPPLY REJECTION ANALOG INPUT1 Input Span (with VREF = 1.0 V)1 (with VREF = 2.5 V) Input (VINA or VINB) Range Input Capacitance1 INTERNAL VOLTAGE REFERENCE1 Output Voltage (1V mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2.5 V Mode) Output Voltage Tolerance (2.5 V Mode) Load Regulation VREF6 Load Regulation LPTVREF1, 6, 7 REFERENCE INPUT RESISTANCE 1, 2, 3 1, 2, 3 1, 2, 3 SUBGROUPS 1 9, 10, 11 MIN 14 10 ----3.0 ------3 --1.5 --0.75 ---1, 2, 3 -2 -0 --------1, 2, 3 -TYP1 --0.9 0.36 ± 2 .5 ± 0 .6 ± 2 .5 ± 0 .7 ---3.0 20.0 5.0 -----16 1 -2.5 -10 -5 MAX ----+3.0 ± 1 .0 --14 +3 1.5 0.75 ---0 .1 -5 -AVDD +.25 --± 14 -± 35 -10.0 -UNIT Bits MHz LSB rms LSB rms LSB LSB LSB LSB Bits Guaranteed % FSR % FSR % FSR ppm/° C ppm/° C ppm/° C % FSR V p-p V p-p V V pF Volts mV Volts mV mV mV k
1 1 -1 1, 2, 3
Memory
1, 2, 3
---
06.13.02 Rev 5
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
9240LP
TABLE 4. 9240LP DC SPECIFICATIONS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2 K, VREF = 2.5V,VINA = VINB =± 2.5V DIFFERENTIAL INPUT CENTERED ON VREF(1.25V TO 3.75V ABSOLUTE), TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED)
PARAMETER LPT ASIC RDS ON - VREF - VIN A - VIN B LATCHUP PROTECTION - Decision Time - Protect Time - AVDD Trip Current - AVDD Trip Current Tolerance - DVDD Trip Current - DVDD Trip Current Tolerance POWER SUPPLIES Supply Voltages - AVDD - DVDD - DRVDD Supply Current - IAVDD - IDVDD POWER CONSUMPTION8 1. Guaranteed by design. 2. Tested using external VREF with servo control 3. VREF = 1V 4. Including internal reference. 5. Excluding internal reference. 6. Load regulation with 1 mA load current. 7. LPTVREF should not be capacitively loaded above 0.1 µ F. 8. Calculated from IDD SUBGROUPS 1, 2, 3 ---8 8 105 105 10 70 75 ± 15 28 ±5 15 ---------ohm ohm ohm ohm µs µs mA mA mA mA MIN TYP1 MAX UNIT
-------
Memory
----
5 5 5
----
V (±5% AVDD Operating) V (±5% DVDD Operating) V (±5% DRVDD Operating)
1, 2, 3 1, 2, 3 1, 2, 3
---
43 3 295
55 16 355
mA mA mW
06.13.02 Rev 5
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies All rights reserved.
Others parts begin by 92
92-1
|
|
|
