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Details, datasheet, quote on part number:97SD3240
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| Part: | 97SD3240 |
| Category: | Memory => DRAM => SDR SDRAM => 1 Gb |
| Description: | 1.25 GB (8-Meg X 40-Bit X 4 Banks)<<<>>>Features<<<>>><<<>>>1.25 Gigabit ( 8-Meg X 40-Bit X 4-Banks) <<<>>>RAD-PAK Radiation-hardened Against Natural Space Radiation <<<>>>Total Dose Hardness:<<<>>>>100 Krad (Si), Depending Upon Space Mission <<<>>>Excellent Single Event Effects:<<<>>>selth > 85 MeV/mg/cm2 @ 25 C <<<>>>JEDEC Standard 3.3V Power Supply <<<>>>Clock Frequency: 100 MHZ Operation <<<>>>Operating Tremperature: -55 to +125 C <<<>>>Auto Refresh <<<>>>Single Pulsed Ras <<<>>>2 Burst Sequence Variations<<<>>>sequential (BL =1/2/4/8)<<<>>>Interleave (BL = 1/2/4/8) <<<>>>Programmable Cas Latency: 2/3 <<<>>>Power Down And Clock Suspend Modes <<<>>>LVTTL Compatible Inputs And Outputs <<<>>>Package: 132 Lead Quad Stack Pack Flat Package <<<>>>Description<<<>>><<<>>>Maxwell Technologies Synchronous Dynamic Random Access Memory (SDRAM) is Ideally Suited For Space Applications Requiring High Performance Computing And High Density Memory Storage. As Microprocessors Increase in Speed And Demand For Higher Density Memory Escalates, Sdram Has Proven to be The Ultimate Solution BY Providing Bit-counts up to 1.25 Gigabits And Speeds up to 100 Megahertz. Sdrams Represent a Significant Advantage in Memory Technology Over Traditional DRAMs Including The Ability to Burst Data Synchronously at High Rates With Automatic Column-address Generation, The Ability to Interleave Between Banks Masking Precharge Time. |
| Company: | Maxwell Technologies |
| Datasheet: | Download 97SD3240 datasheet File size : 779 kB |
| Request For quote: | Find where to buy 97SD3240
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Datasheet text preview:
97SD3240
1.25Gb SDRAM
8-Meg X 40-Bit X 4-Banks
Logic Diagram (One Amplifier)
Memory
FEATURES:
· 1.25 Gigabit ( 8-Meg X 40-Bit X 4-Banks) · RAD-PAK® radiation-hardened against natural space radiation · Total Dose Hardness: >100 krad (Si), depending upon space mission · Excellent Single Event Effects: SELTH > 85 MeV/mg/cm2 @ 25°C · JEDEC Standard 3.3V Power Supply · Clock Frequency: 100 MHz Operation · Operating tremperature: -55 to +125 °C · Auto Refresh · Single pulsed RAS · 2 Burst Sequence variations Sequential (BL =1/2/4/8) Interleave (BL = 1/2/4/8) · Programmable CAS latency: 2/3 · Power Down and Clock Suspend Modes · LVTTL Compatible Inputs and Outputs · Package: 132 Lead Quad Stack Pack Flat Package
DESCRIPTION:
Maxwell Technologies' Synchronous Dynamic Random Access Memory (SDRAM) is ideally suited for space applications requiring high performance computing and high density memory storage. As microprocessors increase in speed and demand for higher density memory escalates, SDRAM has proven to be the ultimate solution by providing bit-counts up to 1.25 Gigabits and speeds up to 100 Megahertz. SDRAMs represent a significant advantage in memory technology over traditional DRAMs including the ability to burst data synchronously at high rates with automatic column-address generation, the ability to interleave between banks masking precharge time Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding for a lifetime in orbit or space mission. In a typical GEO orbit, RAD-PAK® provides greater than 100 krads(Si) radiation dose tolerance. This product is available with screening up to Class K.
03.26.04 Rev 1
All data sheets are subject to change without notice
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(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2004 Maxwell Technologies All rights reserved.
1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM
Pinout Description
97SD3240
Memory
The 97SD3240 Consists of 5, 8-Meg X 8-Bit X 4-Banks, die. The 132 Pin 3-layer stack package contains 2die in layer one and two and one die in layer three. CLK1 clocks die 1, 3 and 5, while CLK2 clocks die 2 and 4. CKE 1-5, CS 1-5 and DQM 1-5 correspond to one of the die: CKE1, CS1 and DQM1 control D0 - D7 CKE2, CS2 and DQM2 control D8 - D15 CKE3, CS3 and DQM3 control D16 - D23 CKE4, CS4 and DQM4 control D24 - D31 CKE5, CS5 and DQM5 control D32 - D39
03.26.04 Rev 1
All data sheets are subject to change without notice
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©2004 Maxwell Technologies All rights reserved.
1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM
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97SD3240
TABLE 1. ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Operating Temperature Storage Temperature SYMBOL VIN VOUT VCC IOUT TOPR TSTG MAX -0.5 to VCC + 0.5 (< 4.6(max)) -0.5 to +4.6 50 -55 to +125 -65 to +150 UNIT V V mA °C °C
TABLE 2. RECOMMENDED OPERATING CONDITIONS
(VCC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
P A R AM ET ER Supply Voltage SYMBOL MIN MAX VCC, VCCQ1,2 3.0 3.6 VSS, VSSQ3 0 0 Input High Voltage VIH1,4 2.0 VCC + 0.3 Input Low Voltage VIL1,5 -0.3 0.8 1. All voltage referred to VSS 2. The supply voltage with all VCC and VCCQ pins must be on the same level 3. The supply voltage with all V SS and V SSQ pins must be on the same level 4. 5. VIH (max) = VCC+2.0V for pulse width <3ns at VCC VIL (min) = VSS-2.0V for pulse width <3ns at VSS UNIT V V V V
Memory
TABLE 3. DELTA LIMITS
PARAMETER ICC1 ICC2P ICC2PS ICC2N ICC2NS DESCRIPTION Operating Current Power Down Standby Current VARIATION1 ± 10% ± 10% ± 10%
Active Standby Current ICC3P ICC3PS ICC3N ICC3NS 1. ± 10% of value specified in Table 4
TABLE 4. DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER Operating Current1,2,3 SYMBOL ICC1 TEST CONDITIONS Burst length CAS Latency = 2 =1 CAS Latency = 3 tRC = min CKE = VIL tCK = 12 ns CKE = VIL tCK = 0 SUBGROUPS 1, 2, 3 MIN MAX 575 575 1, 2, 3 1, 2, 3 15 10 mA mA UNITS mA
Standby Current in Power Down4 Standby Current in Power Down ( input signal stable)5
ICC2P ICC2PS
03.26.04 Rev 1
All data sheets are subject to change without notice
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©2004 Maxwell Technologies All rights reserved.
1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM
TABLE 4. DC ELECTRICAL CHARACTERISTICS
97SD3240
SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 550 725 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 -3 -5 - 1.5 2.4 1100 15 3 5 1 .5 mA mA uA uA uA V MIN MAX 100 45 20 15 150 75 UNITS mA mA mA mA mA mA mA
(VCC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER Standby Current in non power down6 Standby Current in non power down7 ( Input signal stable) Active standby current in1,2,4 power down Active standby current in power down (input signal stable)2,5 Active standby power in non power down1,2,6 Active standby current in non power down ( input signal stable)2,7 Burst Operating Current1,2,8 CAS Latency = 2 CAS Latency = 3 Refresh Current3 Self Refresh current9 SYMBOL ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 TEST CONDITIONS CKE, CS = VIH tCK = 12 ns CKE = VIH tCK = 0 CKE = VIL tCK = 12 ns CKE = VIL tCK = 0 CKE, CS1-6 = VIH tCK = 12 ns CKE = VIH tC K = 0 tCK = min BL = 4 tRC = min VIH>VCC - 0.2V VIL < 0.2 V 0
Memory
ICC5 ICC6 ILI ILI ILO VOH
Input Leakage Current - CLK Input Leakage Current - All Other Output Leakage Current Output high voltage
IOL = 4 mA 1, 2, 3 0.4 V Output low voltage VOL 1. ICC1 depends on output load conditions when the device is selected. ICC1(max) is specified with the output open. 2. One Bank Operation 3. Input signals are changed once per clock. 4. After power down mode, CLK operating current. 5. After power down mode, no CLK operating current. 6. Input signals are changed once per two clocks. 7. Input signals for VIH or VIL are fixed. 8. Input signals are changed once per four clocks. 9. After self refresh mode set, self refresh current. Use Self Refresh for temperatures less than 70 °C ONLY.
03.26.04 Rev 1
All data sheets are subject to change without notice
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©2004 Maxwell Technologies All rights reserved.
1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM
TABLE 5. AC Electrical Characteristics
97SD3240
MIN 10 7.5 TYPICAL MAX UNIT ns
(VCC =3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER System clock cycle time1 (CAS latency = 2) (CAS latency = 3) CLK high pulse width1,7 CLK low pulse width1,7, CLK1,2 Access time from (CAS latency = 2) (CAS latency = 3) SYMBOL tC K SUBGROUPS 9, 10, 11
tC K H tC K L tA C
9, 10, 11 9, 10, 11 9, 10, 11
2.5 2.5 6 6
ns ns ns
Data-out hold time1,2,3 CLK to Data-out low impedance1,2,3,7 impedance1,47, CLK to Data-out high (CAS latency = 2, 3) Input setup time1,5,6 CKE setup time for power down exit1 Input hold time1,6 Ref/Active to Ref/Active command period1 Active to Precharge command period1 Active command to column command (same bank) Precharge to Active command period1 Write recovery or data-in to precharge lead Active( a) to Active (b) command Transition time(rise and Refresh Period fall)7 period1 time1
1
tOH tLZ tHZ tAS, tCS, tDS, tCES tCESP tAH, tCH, tDH tC E H tR C tRAS tRCD tR P tD P L tRRD tT tREF
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 @ 105 °C @ 85 °C
2.7 2 5.4 1.5 1.5 1.5 70 50 20 20 20 20 1 16 32 64 5 6.4 168 120000
ns ns ns ns
Memory
ns ns ns ns ns ns ns ns ns ms
@ 70 °C 128 1. AC measurement assumes tT=1ns. Reference level for timing of input signals is 1.5V. 2. Access time is measured at 1.5V. 3. tLZ(min) definesthe time at which the outputs achieve the low impedance state. 4. tHZ(min) defines the time at which the outputs achieve the high impedance state. 5. tCES defines CKE setup time to CLK rising edge except for the power down exit command. 6. tAS/tAH: Address, tCS/tCH: /RAS, /CAS, /WE, DQM 7. Guarenteed by design (Not tested). 8. Guarenteed by Device Charactreization Testing. (Not 100% Tested)
03.26.04 Rev 1
All data sheets are subject to change without notice
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©2004 Maxwell Technologies All rights reserved.
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