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Part: SY10E196
Category:
Logic
-> Delay Lines
-> Bipolar->ECL 100 Family
Description: Programmable Delay w/ Fine Tune Output
Company: Micrel Semiconductor
Datasheet: Download SY10E196 datasheet File size : 79 kB
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Datasheet text preview:
PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT
ClockWorksTM SY10E196 SY100E196 FINAL
FEATURES
s Up to 2ns delay range s Extended 100E VEE range of 4.2V to 5.5V s s s s s s s
DESCRIPTION
T h e SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjustment organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. The FTUNE input takes an analog coltage and applies it to an internal linear ramp for reducing the 20s resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.
20ps digital step resolution
Linear input for tighter resolution >1GHz bandwidth On-chip cascade circuitry 75Kk input pulldown resistor Fully compatible with Motorola MC10E/100E196 Available in 28-pin PLCC package
PIN CONFIGURATION
NC
18 17
25 24 23 22 21 20 19
D1 D0 LEN VEE IN IN VBB
26 27 28 1 2 3 4 5 6 7 8 9 10 11
D6 D7
D2 D3
D4 D5
TOP VIEW PLCC J28-1
16 15 14 13 12
FTUNE NC VCC VCCO Q Q VCCO
PIN NAMES
Pin IN/IN Function Signal Input Input Enable Mux Select Inputs Signal Output Latch Enable Minimum Delay Set Maximum Delay Set Cascade Signal Linear Voltage Input VCC to Output
EN SET MIN SET MAX
NC
NC
CASCADE
CASCADE
EN D[0:7] Q/Q LEN SET MIN SET MAX CASCADE FTUNE VCCO
Rev.: E
Amendment: /0
1
Issue Date: October, 1998
ClockWorksTM SY10E196 SY100E196
VBB IN IN 1 1 1 1 1 1 EN *1.25 *1.5 LEN Latch 7-Bit Latch D Q LEN SET MIN SET MAX 1 1 0 0 1 0 0 0 4 gates 1 0 8 gates 1 0 16 gates 1
FTUNE
0
Q
1
1
Q
Cascade
Linear Ramp
CASCADE
CASCADE D0 D1 D2 D3 D4 D5 D6 D7
*Delays are 25% or 50% longer than standard (standard = 80ps).
Micrel
BLOCK DIAGRAM
2
Micrel
ClockWorksTM SY10E196 SY100E196
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C Symbol I IH I EE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 130 130 156 156 -- -- 130 130 156 156 -- -- 130 150 156 179 Min. -- Typ. -- Max. 150 -- TA = +25°C Min. Typ. -- Max. 150 -- TA = +85°C Min. Typ. -- Max. 150 Unit µA mA Condition -- --
3
Others parts begin by sy
SY-1 SY-2 SY-3 SY-4 SY-5 SY-6 SY-7 SY-8 SY-9 SY-10 SY-11
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