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Part: SY10E212JCTR
Category:
Description: SY10/100E212 3-BIT Scannable Register
Company: Micrel Semiconductor
Datasheet: Download SY10E212JCTR datasheet File size : 79 kB
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Datasheet text preview:
3-BIT SCANNABLE REGISTER
SY10E212 SY100E212 FINAL
FEATURES
s s s s s s s Scannable version E112 driver Extended 100E VEE range of 4.2V to 5.5V 1025ps max. CLK to Output Dual differential outputs Master Reset Internal 75K input pull-down resistors Fully compatible with industry standard 10KH, 100K ECL levels s Fully compatible with Motorola MC10E/100E212 s Available in 28-pin PLCC package
DESCRIPTION
T h e SY10/100E212 are scannable registered ECL drivers typically used as fan-out memory address drivers for ECL cache driving. In a VLSI array-based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed with control logic w h i c h greatly facilitates its use in boundary scan applications.
PIN CONFIGURATION
NC S-OUT SHIFT MR
VCCO
S-OUT D Q D2 Q2b Q2a Q2a Q2b
25 24 23 22 21 20 19
LOAD CLK D2 VEE D1 D0 S-IN
Q2 b
Q2 a
BLOCK DIAGRAM
26 27 28 1 2 3 4 5 6 7 8 9 10 11
18 17
Q2b Q2a VCC Q1b Q1a Q1b Q1a
TOP VIEW PLCC J28-1
16 15 14 13 12
D Q D1
Q1b Q1a Q1a Q1b
VC C O Q0 a Q0 b Q0 a Data Inputs Scan Input Scan Control Clock Master Reset Scan Output True Outputs
D Q D0 S-IN LOAD SHIFT CLK MR
Q0b Q0a Q0a Q0b
PIN NAMES
Pin D0 D2 S-IN LOAD SHIFT CLK MR S-OUT Q[0:2]a, Q[0:2]b Q[0:2]a, Q[0:2]b VCCO Function
LOAD/HOLD Control
Inverting Outputs VCC to Output
VC C O
Rev.: C
NC
Q0 b
Amendment: /1
1
Issue Date: February, 1998
Micrel
SY10E212 SY100E212
TRUTH TABLE
LOAD L H X X SHIFT L L H X MR L L L H Mode Load Hold Shift Reset
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C Symbol I IH I EE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 80 80 96 96 -- -- 80 80 96 96 -- -- 80 92 96 110 Min. -- Typ. -- Max. 150 Min. -- TA = +25°C Typ. -- Max. 150 -- TA = +85°C Min. Typ. -- Max. 150 Unit µA mA Condition -- --
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C Symbol tPLH tPHL Parameter Propagation Delay to Output CLK MR CLK to S-OUT Set-up Time D SHIFT LOAD S-IN Hold Time D SHIFT LOAD S-IN Reset Recovery Within-Device Skew Within-Gate Skew Rise/Fall Times 20% to 80% Min. 575 575 575 175 150 225 150 250 300 225 300 600 -- -- 275 Typ. 800 800 800 25 50 50 50 25 100 0 100 350 100 50 425 Max. 1025 1025 1025 -- -- -- -- -- -- -- -- -- -- -- 650 Min. 575 575 575 175 150 225 150 250 300 225 300 600 -- -- 275 TA = +25°C Typ. 800 800 800 25 50 50 50 25 100 0 100 350 100 50 425 Max. 1025 1025 1025 -- -- -- -- -- -- -- -- -- -- -- 650 TA = +85°C Min. 575 575 575 175 150 225 150 250 300 225 300 600 -- -- 275 Typ. 800 800 800 25 50 50 50 25 100 0 100 350 100 50 425 Max. 1025 1025 1025 ps -- -- -- -- ps -- -- -- -- -- -- -- 650 ps ps ps ps -- 1 2 -- -- -- Unit ps Condition --
tS
tH
tRR t skew t skew tr tf
NOTES: 1. Within-device skew is defined as identical transitions on similar paths through a device. 2. Within-gate skew is defined as the difference in delays between various outputs of a gate when driven from the same input.
PRODUCT ORDERING CODE
Ordering Code SY10E212JC SY10E212JCTR SY100E212JC SY100E212JCTR 2 Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial
Micrel
SY10E212 SY100E212
28 LEAD PLCC (J28-1)
Rev. 03
3
Others parts begin by sy
SY-1 SY-2 SY-3 SY-4 SY-5 SY-6 SY-7 SY-8 SY-9 SY-10 SY-11
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