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Part: SY10E256JCTR
Category:
Logic
-> Gates
Description: 3-Bit 4:1 Mux-latch
Company: Micrel Semiconductor
Datasheet: Download SY10E256JCTR datasheet File size : 79 kB
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Datasheet text preview:
3-BIT 4:1 MUX-LATCH
SY10E256 SY100E256 FINAL
FEATURES
s 950ps max. data to output s Extended 100E VEE range of 4.2V to 5.5V s s s s 850ps max. latch enable to output Separate select controls Differential outputs Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E256 s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram). When the Latch Enable (LEN) is at a logic LOW, the latch is transparent and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
BLOCK DIAGRAM
D0a D0b D0c D0d
PIN CONFIGURATION
VCCO
18 17 16
D1b
D1a D2d
D2c D2b
D E NR
Q0 Q0
SEL1A SEL1B
26 27 28 1 2 3 4
25 24 23 22 21 20 19
D2a
D1a D1b D1c D1d
Q2 Q2 VC C Q1 Q1 VC C O Q0
D E NR
Q1 Q1
SEL2 VE E LEN MR D 1c
TOP VIEW PLCC J28-1
15 14 13 12
SEL1A SEL1B SEL2 LEN MR
PIN NAMES
Pin D0xD2x SEL1A, SEL1B SEL2 LEN MR Q0, Q0Q2, Q2 VCCO Function Parallel Data Inputs First-stage Select Inputs Second-stage Select Input Latch Enable Master Reset Data Outputs VCC to Output
D 0d VCCO Q0
Rev.: C
D 0a D0b D 0c
D1d
D2a D2b D2c D2d
D E NR
Q2 Q2
5
6
7
8
9
10 11
Amendment: /1
1
Issue Date: February, 1998
Micrel
SY10E256 SY100E256
TRUTH TABLE
Pin SEL2 SEL1A SEL1B State H H H Operation Output c/d Data Input d Data Input b Data
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C Symbol I IH I EE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 69 69 83 83 -- -- 69 69 83 83 -- -- 69 79 83 96 -- -- 150 TA = +25°C -- -- 150 TA = +85°C Max. 150 Unit µA mA Condition -- -- -- -- Min. Typ. Max. Min. Typ. Max. Min. Typ.
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C Symbol tPLH tPHL Parameter Propagation Delay to Output D SEL1 SEL2 LEN MR Set-up Time D SEL1 SEL2 Hold Time D SEL1 SEL2 Reset Recovery Time Minimum Pulse Width, MR Within-Device Skew Rise/Fall Time 20% to 80% TA = +25°C TA = +85°C Max. 900 1050 900 800 825 ps 400 600 500 300 100 200 700 400 -- 275 275 300 250 275 300 250 600 -- 50 475 -- -- -- -- -- -- -- -- -- 700 400 600 500 300 100 200 700 400 -- 275 275 300 250 275 300 250 600 -- 50 475 -- -- -- -- -- -- -- -- -- 700 400 600 500 300 100 100 700 400 -- 275 275 300 250 275 300 250 600 -- 50 475 -- -- -- ps -- -- -- -- -- -- 700 ps ps ps ps -- -- 1 -- -- -- Unit ps 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 Condition -- Min. Typ. Max. Min. Typ. Max. Min. Typ.
tS
tH
tRR t PW t skew tr tf
NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering Code SY10E256JC SY10E256JCTR SY100E256JC SY100E256JCTR 2 Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial
Micrel
SY10E256 SY100E256
28 LEAD PLCC (J28-1)
Rev. 03
3
Others parts begin by sy
SY-1 SY-2 SY-3 SY-4 SY-5 SY-6 SY-7 SY-8 SY-9 SY-10 SY-11
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