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Part: ML6622CS
Category:
Description: High Speed Quantizer
Company: Micro Linear
Datasheet: Download ML6622CS datasheet File size : 123 kB
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March 1997
Micro Linear
ML6622* High-Speed Data Quantizer
GENERAL DESCRIPTION
The ML6622 high-speed data quantizer (post-amplifier) is a low noise, wide-band, BiCMOS monolithic IC designed for high-speed signal recovery applications, such as FDDI, Fast Ethernet, and ATM. An internal DC restoration feedback loop nulls any offset voltage produced in the input stage. The limiting amplifier contributes to a high level of sensitivity and a minimum of duty cycle distortion. The output of the data path is a high-speed comparator with ECL outputs. An enable pin gates the comparator on or off in response to the input signal level or a system control signal. The Link Detect circuit provides an Assert-Deassert function with a user-selectable threshold voltage. This circuit monitors the input signal and provides an ECL High output within 100ms of signal acquisition and an ECL Low output within 350ms of signal loss. The ECL discriminator output can be used to disable the comparator when the signal is below the user-selected threshold. LINKLED drives an LED for a visible indication of the link status.
FEATURES
s s s s s
200 MHz bandwidth Low noise design Adjustable Link Detect function Low power design: 35mA typical Used with the ML6633 LED driver
APPLICATIONS
FDDI Fast Ethernet, 100BASE-FX s ATM (SONET), 155Mbps s Fibre Channel, 133 or 266Mbps s Proprietary high-speed fiber optic data links
s s
*Some Packages Are Obsolete
BLOCK DIAGRAM
VCCA 14 VIN+ 13 AMP VIN 12 ECL CMP GNDA 11 VCC 3 GND 6 4 ECL OUT+ 5 ECL OUT
FILTER
1 ENABLE
LINK DETECT 7 LINK+ VREF 9 REF THRESH TIMER LINK OUT
8 LINK
15 CAP
10 THIN
16
2
CTIME LINKLED
Micro Linear
1
ML6622
PIN DESCRIPTION
PIN# 1 NAME ENABLE FUNCTION ECL input active low. When this input is tied to LINKLED the ECL comparator output is automatically enabled and disabled by the Link Detect circuit. This input can be tied to GND for continuous enable. When the ECL Comparator is disabled, ECL OUT goes low and ECL OUT+ goes high. Link Detect Status output. LINKLED is an open collector active low signal. It will be active low when the input signal applied to VIN+,VIN exceeds the programmed threshold level at the THIN pin. Capable of driving a 20mA LED indicator. Positive Power Supply. +5 volts Positive and Negative ECL Comparator outputs. 1mA internal pull downs are incorporated. Ground connection. Used for less noise sensitive nodes. Positive ECL Link Detect output. Active high when the input signal exceeds the programmed Link Detect threshold. 1mA internal pull down current sources. Negative ECL Link Detect output. Active low when the input signal exceeds the programmed Link Detect threshold. 1mA internal pull down current sources. A 2.5V reference with respect to GND. NAME PIN # 10 THIN FUNCTION Threshold Input. A voltage applied to this input pin sets the minimum amplitude of the input signal required to cause the link detect to activate. In most cases this can be tied to VREF. Ground connection for noise sensitive circuits in the chip; the input amplifier, DC restoration loop, part of the Comparator and part of the link detect circuit. In some system designs, it may be advantageous to separate GND and GNDA. This input pin should be capacitively coupled to the input source or to VCCA. This input pin should be capacitively coupled to the input source or to VCCA. Positive power supply VCC for noise sensitive circuits as mentioned in GNDA. +5 volts. A capacitor is tied from this pin to VREF. This capacitor sets the lower frequency rejection and helps remove internal DC offset. This capacitor should be 10 times larger than the input capacitors. A capacitor from this pin to ground determines the Link Detect response time. To Meet FDDI specifications this capacitor should be 2,000pF. This capacitor can be removed for faster response time.
11
GNDA
2
LINKLED
12 13 14
VIN VIN+ VCC A
3
VCC
4 ECL OUT+ 5 ECL OUT 6 7 GND LINK+
15
CAP
16
8
LINK
CTIMER
9
V REF
PIN CONNECTION
ML6622 16-Pin Narrow SOIC (S16N)
ENABLE LINKLED VCC ECL OUT+ ECL OUT GND LINK+ LINK
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
CTIMER CAP VCCA VIN+ VIN GNDA THIN VREF
TOP VIEW
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Micro Linear
ML6622
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC ....... GND 0.3V to 6V VCCA ..... GND 0.3V to 6V Inputs/Outputs .. GND 0.3V to VCC + 0.3 Junction Temperature ............ 150°C Storage Temperature Range .... 65°C to 150°C Lead Temperature (Soldering 10 sec.) .... 260 °C Thermal Resistance .......... 100°C/W
ELECTRICAL CHARACTERISTICS
SYMBOL ICC VREF IVREF VIN VTH ADJ Range EN RIN ITHIN VOL-VCC VOH-VCC PARAMETER VCC Supply Current Reference Voltage VREF Output Current Input Signal Range External Voltage at THIN to set VTH Input-referred Voltage Noise Input Resistance Input Bias Current of THIN ECL Output Voltage-Low ECL Output Voltage-High
Unless otherwise specified, VCC = V CC = 5V ± 10%, TA = Operating Temperature Range. (Note 1)
CONDITIONS No load on ECL outputs 2.30 1 3.5 0.5 100 MHz BW VIN+, VIN 500 100 Through 50 to VCC 2V Through 50 to VCC 2V C Suffix I Suffix tr tf Link Detect AS_Max ANS_Max VTH BW VIPW DCD DDJ
Note 1:
MIN
TYP 35 2.47 3
MAX 50 2.57 +5 1600 VREF
UNITS mA V mA mVP-P V µVRMS
25 770 1500 +100 1.730 0.963 0.963 1.620 0.800 0.780 1.3 1.3
µA V V V ns ns
1.810 1.025 1.025 0.5 0.5
Data Output Rise Time Data Output Fall Time
Assert Time (off to on) Deassert Time (on to off) Input threshold Hysteresis Bandwidth 1-3dB Minimum Input Pulse Width Duty Cycle Distortion Peak-to-peak Data Dependent Jitter Peak-to-peak
CTIME = 2000pF CTIME = 2000pF THIN = VREF Assert
0 0 8 1.5 10 1.7 200 5
100 350 12 2
µs µs mV dB MHz ns ns ns
Data rate = 155Mb/s 50% duty cycle input FDDI 56 Data Pattern VIN = 60mV, Data rate = 125Mb/s
0.5 1.2
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case conditions.
Micro Linear
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