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Part: ML6691
Category:
Communication
-> Network
-> Ethernet/DS1/E1 (T1/E1)
Description: 100base-t Mii-to-pmd Transceiver
Company: Micro Linear
Datasheet: Download ML6691 datasheet File size : 123 kB
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Datasheet text preview:
March 1997
ML6691* 100BASE-T MII-to-PMD Transceiver
GENERAL DESCRIPTION
The ML6691 implements the upper portion of the physical layer for the Fast Ethernet 100BASE-T standard. Functions contained in the ML6691 include a 4B/5B encoder/ decoder, a Stream Cipher scrambler/descrambler, and collision detect. Additional functions of the ML6691 -- accessible through the two-wire MII management interface -- include full duplex operation, loopback, power down mode, and MII isolation. The ML6691 is designed to interface to a 100BASE-T Ethernet Media Access Controller (MAC) via the MII (Media Independent Interface) on one side, and a 100BASE-X PMD transceiver on the other side. A complete 100BASE-TX physical layer (PHY) solution is realized using the ML6691, the ML6673, and one of the available clock recovery/generation devices. A 100BASEFX physical layer solution is implemented by disabling the scrambler function of the ML6691 and using an external optical PMD.
FEATURES
s s s s s s s s s
Conforms to the Fast Ethernet 100BASE-T IEEE 802.3µ standard Integrated 4B/5B encoder/decoder Integrated Stream Cipher scrambler/descrambler Compliant MII interface Two-wire serial interface management port for configuration and control On-chip 25 MHz crystal oscillator Interfaces to either AMD's PDT/PDR (AM79865/79866) or Motorola's FCG (MC68836) Used with ML6673 for 100BASE-TX solutions 44-pin PLCC package * This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
TXC OSC
VCC
GND
TXCLK TXD3 ... TXD0
NIBBLE INPUT REGISTER
4B/5B ENCODER
STREAM CIPHER SCRAMBLER
SYMBOL OUTPUT REGISTER
TSM4 ... TSM0
SD TXEN TXER COL CRS RXDV RXER TRANSMIT STATE MACHINE COLLISION DETECTION RECEIVE STATE MACHINE DCFR
RXCLK RXD3 ... RXD0
NIBBLE OUTPUT REGISTER
5B/4B DECODER
SYMBOL ALIGNER
STREAM CIPHER DESCRAMBLER
SYMBOL INPUT REGISTER
RSM4 ... RSM0 RXC
ISOLATE
FULLDUP
COLTST
LPBK
LINK FAILED
MDIO MDC
MANAGEMENT SECTION CONTROL STATUS
CS LPBK
LOCAL
AD4...AD0
RST
1
ML6691
PIN CONFIGURATION
ML6691 44-PIN PLCC (Q44)
TXCLK MDIO 41 TXEN MDC AD4 AD3 AD2 AD1 AD0 T XC 40 39 TSM4 38 TSM3 37 TSM2 36 TSM1 35 TSM0 34 SD 33 RSM4 32 RSM3 31 RSM2 30 RSM1 29 RSM0 18 RXDV 19 20 RXER RXCLK 21 VCC 22 DCFR 23 GND 24 LOCAL 25 RST 26 CS 27 LPBK 28 RXC VCC 1
6 TXER 7 TXD3 8 TXD2 9 TXD1 10 TXD0 11 CRS 12 COL 13 RXD3 14 RXD2 15 RXD1 16 RXD0 17
5
4
3
2
44
43
42
PIN DESCRIPTION
PIN# NAME FUNCTION PIN# NAME FUNCTION
1,21 2,3,4, 43,44
VCC AD[4:0]
Positive 5 volt supply. Local PHY address. These 5 inputs set the address to which the local physical layer responds. When an address match is detected, the CS output is asserted. Transmit clock output. Continuous 25MHz clock provides the timing reference for the transfer of TXEN, TXER, and TXD[3:0] from the MAC. TXCLK is generated from the TXC input. Transmit enable input. A logic high enables the transmit section of the ML6691. This signal indicates the MAC is transmitting nibble-wide data. TXEN is synchronous to TXCLK. Transmit error input. When TXER is high , while TXEN is asserted, the ML6691 will insert an "H" symbol in the data stream. TXER is synchronous to TXCLK.
12
CRS
Carrier sense output. A logic high indicates that either the transmit or receive medium is non-idle. CRS is deasserted when both transmit and receive are idle. Collision detect output. A logic high indicates a collision (simultaneous transmit and receive in half duplex mode).
13
COL
5
TXCLK
14-17
6
TXEN
RXD[3:0] Receive nibble data outputs. Nibblewide data for transmission to the MAC. RXD[0] is the least significant bit. RXD[3:0] is synchronous to RXCLK. RXDV Receive data valid output. A logic high indicates the ML6691 is presenting valid nibble-wide data. RXDV shall remain asserted from the first recovered nibble of the frame through the final recovered nibble. RXDV will be de-asserted prior to the first RXCLK that follows the final nibble. RXDV is synchronous to RXCLK. Receive error output. Active high, indicates that a coding error was detected. RXER is synchronous to RXCLK.
18
7
TXER
8-11
TXD[3:0] Transmit nibble data inputs. Nibblewide data from the MAC. For data transmission TXEN must be asserted. TXD[0] is the least significant bit. TXD[3:0] is synchronous to TXCLK.
19
RXER
2
ML6691
PIN DESCRIPTION (Continued)
PIN# NAME FUNCTION PIN# NAME FUNCTION
20
RXCLK
Receive clock output. Continuous 25 MHz clock provides the timing reference for the transfer of RXDV, RXER, and RXD[3:0] to the MAC. Scrambler/descrambler disable. A logic high on this input disables the Stream Cipher scrambler/descrambler. Ground Local/remote. A logic low on this input places the ML6691 in remote mode, in which the MII interface is disabled at power on or after a reset operation. When low, the isolate bit of the Control register will be set upon power up or reset. Reset. A logic high on this input resets the Status and Control registers to their default states. Chip select. A logic low is generated on this output when the ML6691 detects an address match. Loopback. A logic low on this output indicates the loopback function. Receive symbol clock. A 25 MHz clock input from the PMD layer. The rising edge of RXC is used to sample RSM[4:0].
29-33
RSM[4:0] Receive symbol data inputs. Symbolwide (encoded) data from the PMD layer. SD Signal detect. A logic high on this input indicates the presence of nonquiet data. The internal signal, linkfail, is enabled 330µs after SD is asserted.
34
22
DCFR
23 24
GND LOCAL
35-39
TSM[4:0] Transmit symbol data outputs. Symbolwide (encoded) data for transfer to the PMD layer. TXC Transmit symbol clock input. Input used to generate TXCLK. Use either a 25 MHz crystal or a 25 MHz clock between TXC input and GND. Management data input/output. A bi-directional signal used to transfer control and status information between the ML6691 and the MAC. MDIO is synchronous to MDC. Management data clock input. A lowfrequency aperiodic clock used as the timing reference for transfer of information on the MDIO signal.
40
41
MDIO
25
RST
26
CS
42
MDC
27 28
LPBK RXC
3
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