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Part: ML6692CH
Category:
Description: 100BASE-TX Fast Ethernet Physical Layer
Company: Micro Linear
Datasheet: Download ML6692CH datasheet File size : 123 kB
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April 1999
ML6692 100BASE-TX Physical Layer with MII
GENERAL DESCRIPTION
The ML6692 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6692 interfaces to the controller through the standard-compliant Media Independent Interface (MII). The ML6692 functionality includes auto-negotiation, 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive equalization, baseline wander correction, and MLT-3/ 10BASE-T transmitter. For applications requiring 100Mbps only, such as repeaters, the ML6692 offers a single-chip per-port solution. For 10/100 dual speed adapters or switchers, 10BASE-T functionality may be attained using Micro Linear's ML2653, or by using an Ethernet controller that contains an integrated 10BASE-T PHY.
F E AT U R E S
s s s s
Single-chip 100BASE-TX physical layer Compliant to IEEE 802.3u 100BASE-TX standard Supports adapter, repeater and switch applications Single-jack 10BASE-T/100BASE-TX solution when used with external 10Mbps PHY Compliant MII (Media Independant Interface) Auto-negotiation capability 4B/5B encoder/decoder Stream Cipher scrambler/descrambler 125MHz clock recovery/generation Baseline wander correction Adaptive equalization and MLT-3 encoding/decoding Supports full-duplex operation
s s s s s s s s
BLOCK DIAGRAM
1 9
(PLCC Package)
49 48
CLOCK SYNTHESIZER
TXCLK
3 4 5 6 7 8 18 19 17 10 12 14 16 21 23 24 25
TXD3 TXD2 TXD1 TXD0 TXEN TXER CRS COL RXCLK RXD3 RXD2 RXD1
PCS TRANSMIT STATE MACHINE 4B/5B ENCODER SCRAMBLER NRZ TO NRZI ENCODER SERIALIZER MLT-3 ENCODER FLP/100BASE-TX/10BASE-T TWISTED PAIR DRIVER
10BTTXINP
TXCLKIN
10BTTXINN
TPOUTP TPOUTN RTSET
40 39 37
CARRIER AND COLLISION LOGIC
CLOCK AND DATA RECOVERY NRZI TO NRZ DECODER DESERIALIZER
EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX
TPINP TPINN CMREF RGMSET LINK100
45 44 46 36 43
PCS RECEIVE STATE MACHINE 5B/4B DECODER
RXD0 RXDV RXER DESCRAMBLER
AUTO-NEGOTIATION AND CONTROL LOGIC 10BTLNKEN
INITIALIZATION REGISTER
10BTRCV
MDIO
T4FAIL
MII MANAGEMENT REGISTERS
29
30
50
51
SEL10HD
T4EN
EDIN
MDC
47
31
32
33
SEL10FD /ECLK
35
SEL100T4 /EDOUT
DUPLEX
1
ML6692
PIN CONFIGURATION
ML6692 52-Pin PLCC (Q52)
TXEN T X D0 T X D1 T X D2 T X D3 AGND1 TXCLKIN AVCC1 10BTLNKEN 10BTRCV 1 0 B T T X IN P 1 0 B T T X IN N DUPLEX
7 6 5 4 3 2 1 52 51 50 49 48 47 TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS COL DGND3 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 46 45 44 43 42 41 40 39 38 37 36 35 34 CMREF TPINP TPINN LINK100 AVCC2 AGND2 TPOUTP TPOUTN AGND3 RTSET RGMSET SEL100T4/EDOUT AVCC3
2
RXDV DVCC2 RXER MDC MDIO DGND4 DVCC5 DGND5 T4EN T4FAIL EDIN SEL10HD SEL 10FD/ECLK
TOP VIEW
ML6692
PIN CONFIGURATION
ML6692 64-Pin TQFP (H64-10)
10BTLNKEN 10BTTXINP 10TTXINN AGND1A AGND1B TXCLKIN 10TRCV AVCC1
TXD0
TXD1
TXD2
TXD3
TXEN
TXER
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TXCLK RXD3 DGND1A DGND1B RXD2 DVCC1A DVCC1B RXD1 DGND2A DGND2B RXD0 RXCLK CRS COL DGND3A DGND3B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DUPLEX CMREF TPINP TPINN LINK100 AVCC2 AGND2A AGND2B TPOUTP TPOUTN AGND3A AGND3B RTSET RGMSET SEL100T4/EDOUT AVCC3
MDC
DGND4A
DVCC5A
MDIO
DGND4B
DVCC5B
DGND5A
T4EN
T4FAIL
DGND5B
EDIN
SEL10HD
TOP VIEW
SEL10FD/ECLK
DVCC2
RXDV
RXER
NC
3
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