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Details, datasheet, quote on part number:24AA16
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| Part: | 24AA16 |
| Category: | Memory => ROM => EEPROM => Serial => I2C->16K to 32K |
| Description: | The 24AA16 is a 16K Bit Electrically Erasable Prom Memory Organized as Eight Blocks of 256 X 8-bit Memory With an I2C™ Compatible 2-wire Serial Interface Bus |
| Company: | Microchip Technology, Inc. |
| Datasheet: | Download 24AA16 datasheet File size : 466 kB |
| Request For quote: | Find where to buy 24AA16
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Datasheet text preview:
24AA16/24LC16B
16K I2CTM Serial EEPROM
Device Selection Table
Part Number 24AA16 24LC16B Note 1: Vcc Range 1.8-5.5 2 .5-5.5 Max Clock Frequency 400 kHz(1) 4 0 0 kH z Temp Ranges I I, E
Description
The Microchip Technology Inc. 24AA16/24LC16B (24XX16*) is a 16 Kbit Electrically Erasable PROM. The device is organized as eight blocks of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.8V with standby and active currents of only 1 µA and 1 mA, respectively. The 24XX16 also has a page write capability for up to 16 bytes of data. The 24XX16 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP and MSOP packages and is also available in the 5-lead SOT-23 package.
100 kHz for VCC <2.5V
Features
· Single supply with operation down to 1.8V · Low-power CMOS technology - 1 mA active current typical - 1 µA standby current (max.) (I-temp) · Organized as 8 blocks of 256 bytes (8 x 256 x 8) · 2-wire serial interface bus, I2CTM compatible · Schmitt Trigger inputs for noise suppression · Output slope control to eliminate ground bounce · 100 kHz (2.5V) and 400 kHz (2.5V) compatibility · Self-timed write cycle (including auto-erase) · Page write buffer for up to 16 bytes · 2 ms typical write cycle time for page write · Hardware write-protect for entire memory · Can be operated as a serial ROM · Factory programming (QTP) available · ESD protection > 4,000V · 1,000,000 erase/write cycles · Data retention > 200 years · 8-lead PDIP, SOIC, TSSOP and MSOP packages · 5-lead SOT-23 package · Standard and Pb-free finishes available · Available temperature ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C
Package Types
PDIP/SOIC/TSSOP/MSOP
A0 A1 A2 Vss 1 8 Vcc WP SCL 2 3 4 7 6 5 SCL Vss 1 2 3
SOT-23-5
5 WP
24XX16
24XX16
SDA SDA
4
Vcc
Note:
Pins A0, A1 and A2 are not used by the 24LC16B. (No internal connections).
Block Diagram
WP HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
I/O SDA
SCL
YDEC
VCC VSS
SENSE AMP R/W CONTROL
*24XX16 is used in this document as a generic part number for the 24AA16/24LC16B devices.
2003 Microchip Technology Inc.
DS21703C-page 1
24AA16/24LC16B
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings ()
VCC ........... 6.5V All inputs and outputs w.r.t. VSS ......... -0.3V to VCC +1.0V Storage temperature ............. -65°C to +150°C Ambient temperature with power applied ...... -65°C to +125°C ESD protection on all pins ............ 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
1.1
DC Characteristics
VCC = +1.8V to +5.5V Industrial (I): TAMB = -40°C to +85°C Automotive (E): TAMB = -40°C to +125°C M in
--
DC CHARACTERISTICS Param. Symbol No. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 VIH -- VIL VHYS VOL ILI ILO CIN, COUT ICC read ICCS Standby current
Characteristic WP, SCL and SDA pins High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs)
Typ -- -- -- -- -- -- -- -- -- 0 .01 0.3 .01
M ax -- -- 0.3 VCC -- 0.40 ±10 ±10 10 3 1 1 5
Units -- V V V V µA µA pF mA mA µ µ -- -- --
Conditions
0.7 VCC -- .05 VCC -- -- -- -- -- -- -- --
(Note 1) IOL = 3.0 mA, VCC = 2.5V VIN =.1V to VCC VOUT =.1V to VCC VCC = 5.0V (Note 1) TAMB = 25°C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz -- Industrial Automotive SDA = SCL = VCC WP = VSS
ICC write Operating current
Note 1: 2:
This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature.
DS21703C-page 2
2003 Microchip Technology Inc.
24AA16/24LC16B
1.2
AC Characteristics
VCC = +1.8V to +5.5V Industrial (I): TAMB = -40°C to +85°C Automotive (E): TAMB = -40°C to +125°C Characteristic Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time Min -- -- 600 4000 1300 4700 -- -- -- 600 4000 600 4700 0 100 250 600 4000 -- -- 1300 4700 2 0 + 0 . 1 CB -- -- -- 1M Max 400 100 -- -- -- -- 300 1000 300 -- -- -- -- -- -- -- -- -- 900 3500 -- -- 250 250 50 5 -- Units kHz ns ns ns Conditions 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) 2.5V VCC 5.5V (Note 1) 1.8V VCC < 2.5V (24AA16) (Note 1) (Note 1) 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) (Note 2) 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) 2.5V VCC 5.5V 1.8V VCC < 2.5V (24AA16) 2.5V VCC 5.5V 1.8V VCC <2.5V (24AA16) (Notes 1 and 3) -- AC CHARACTERISTICS Param. Symbol No. 1 2 3 4 FCLK
THIGH
TLOW TR
5 6 7 8 9 10 11 12
TF
ns ns ns ns ns ns ns ns
THD:STA START condition hold time TSU:STA START condition setup time
THD:DAT Data input hold time TSU:DAT Data input setup time TSU:STO STOP condition setup time TAA TBUF Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) E ndurance
13 14 15 16 Note 1: 2:
TOF TSP TWC --
ns ns ms
cycles 25°C, (Note 4)
3: 4:
Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained on Microchip's web site: www.microchip.com.
2003 Microchip Technology Inc.
DS21703C-page 3
24AA16/24LC16B
FIGURE 1-1: BUS TIMING DATA
5 3 SCL 7 SDA IN 6 14 11 SDA OUT 12 8 9 10 2 4
FIGURE 1-2:
BUS TIMING START/STOP
D4
SCL 7 SDA 6 10
START
STOP
DS21703C-page 4
2003 Microchip Technology Inc.
24AA16/24LC16B
2.0 FUNCTIONAL DESCRIPTION
3.4 Data Valid (D)
The 24XX16 supports a bi-directional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions, while the 24XX16 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device and is, theoretically unlimited, (although only the last sixteen will be stored when doing a write operation). When an overwrite does occur it will replace data in a first-in firstout (FIFO) fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: · Data transfer may be initiated only when the bus is not busy. · During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24XX16 does not generate any Acknowledge bits if an internal programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock (SCL) is high determines a START condition. All commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock (SCL) is high determines a STOP condition. All operations must be ended with a STOP condition.
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX16) will leave the data line high to enable the master to generate the STOP condition.
FIGURE 3-1:
(A) SCL
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B) (D) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE
STOP CONDITION
2003 Microchip Technology Inc.
DS21703C-page 5
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