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Details, datasheet, quote on part number:24AA160-ISN
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Datasheet text preview:
25AA080/160
8K/16K 1.8V SPITM Bus Serial EEPROM
FEATURES
· 3 MHz Clock Rate · SPI Modes 0,0 and 1,1. · Single supply with programming operation down to 1.8V · Low Power CMOS Technology - Max Write Current: 5 mA - Read Current: 1.0 mA - Standby Current: 1 µA typical · Organization - 1024 x 8 for 25AA080 - 2048 x 8 for 25AA160 · 16 Byte Page · Self-timed ERASE and WRITE Cycles · Sequential Read · Block Write Protection - Protect none, 1/4, 1/2, or all of Array · Built-in Write Protection - Power On/Off Data Protection Circuitry - Write Latch - Write Protect Pin · High Reliability - Endurance: 10M cycles (guaranteed) - Data Retention: >200 years - ESD protection: >4000 V · 8-pin PDIP/SOIC Packages · Temperature ranges supported - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C
PACKAGE TYPES
PDIP CS SO WP Vss 1 25AA080/160 2 3 4 8 7 6 5 Vcc HOLD SCK SI
SOIC CS SO WP Vss 1 25AA080/160 2 3 4 8 7 6 5 Vcc HOLD SCK SI
BLOCK DIAGRAM
Status Register HV Generator
DESCRIPTION
The Microchip Technology Inc. 25AA080/160 are 8K and 16K bit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. There are two other inputs that provide the end user with additional flexibility. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. Also write operations to the Status Register can be disabled via the write protect pin (WP).
WP SI SO CS SCK HOLD Sense Amp. R/W Control Y Decoder EEPROM I/O Control Logic Memory Control Logic X Dec Page Latches Array
Vcc Vss
SPI is a trademark of Motorola.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21146D-page 1
25AA080/160
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
FIGURE 1-1:
AC TEST CIRCUIT
Vcc
VCC ..... 7.0V All inputs and outputs w.r.t. ...... VSS-0.6V to VCC +1.0V Storage temperature ..... -65°C to 150°C Ambient temperature under bias..-65°C to 125°C Soldering temperature of leads (10 seconds) ... +300°C ESD protection on all pins..... 4kV
*Notice: Stresses above those listed under `Maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended period of time may affect device reliability.
2.25 K SO 1.8 K 100 pF
1.2
AC Test Conditions
TABLE 1-1:
Name CS SO SI SCK WP VSS VCC HOLD
PIN FUNCTION TABLE
Function Chip Select Input Serial Data Output Serial Data Input Serial Clock Input Write Protect Pin Ground Supply Voltage Hold Input
AC Waveform: VLO = 0.2V VHI = Vcc - 0.2V VHI = 4.0V
(Note 1) (Note 2)
Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC 4.0V 2: For VCC > 4.0V
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted. VCC = +1.8V to 5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Parameter High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Internal Capacitance (all inputs and outputs) Operating Current Symbol VIH1 VIH2 VIL1 VIL2 VOL VOH ILI ILO CINT ICC WRITE Min 2.0 0.7 VCC -0.3 -0.3 -- VCC-0.5 -10 -10 -- Max VCC+1 VCC+1 0.8 0.3 VCC 0.4 -- 10 10 7 Units V V V V V V µA µA pF mA mA mA µA µA µA Test Conditions VCC 2.7V VCC< 2.7V VCC 2.7V VCC< 2.7V IOL=2.1 mA IOH=-400 µA CS=VIH, VIN=VSS to VCC CS=VIH, VOUT=VSS to VCC Tamb=25°C, FCLK=3.0 MHz, VCC=5.5V (Note) VCC=5.5V VCC=2.5V VCC=5.5V; 3 MHz VCC=2.5V; 2 MHz CS=VCC=5.5V; Vin=0V or VCC CS=VCC=2.5V; Vin=0V or VCC
-- 5 -- 3 ICC READ -- 1 -- 500 Standby Current ICCS -- 5 -- 2 Note: This parameter is periodically sampled and not 100% tested.
DS21146D-page 2
Preliminary
© 1996 Microchip Technology Inc.
25AA080/160
FIGURE 1-2: SERIAL INPUT TIMING
tCSD CS tCSS SCK tSU SI MSB in tHD LSB in tR tF tCSH tCLD
SO
high impedance
FIGURE 1-3:
CS
SERIAL OUTPUT TIMING
tHI SCK tV SO MSB out
tLO
tCSH
tHO
tDIS LSB out
SI
don't care
FIGURE 1-4:
CS
HOLD TIMING
tHS SCK
tHH
tHS
tHH
tHZ SO n+2 n+1 n high impedance
tHV n tSU n n-1 n-1
don't care SI HOLD n+2 n+1 n
© 1996 Microchip Technology Inc.
Preliminary
DS21146D-page 3
25AA080/160
TABLE 1-3: AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted. VCC = +1.8V to 5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Symbol fSCK Parameter Clock Frequency Min -- -- -- 100 250 500 100 250 500 250 500 500 30 50 50 50 100 100 -- -- 150 250 475 150 250 475 50 -- -- -- 0 -- -- -- 100 100 200 100 100 200 100 150 200 100 150 200 -- 10M Max 3 2 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 2 -- -- -- -- -- -- -- 150 250 475 -- 200 250 500 -- -- -- -- -- -- -- -- -- -- -- -- 5 -- Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms E/W Cycles Test Conditions VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V (Note 1) (Note 1) VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V (Note 1) VCC=2.5V to 4.5V (Note 1) VCC=1.8V to 2.5V (Note 1) VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=1.8V to 2.5V VCC=4.5V to 5.5V (Note 1) VCC=2.5V to 4.5V (Note 1) VCC=1.8V to 2.5V (Note 1) VCC=4.5V to 5.5V (Note 1) VCC=2.5V to 4.5V (Note 1) VCC=1.8V to 2.5V (Note 1) (Note 2) 25°C, Vcc = 5.0V, Block Mode (Note 3)
tCSS
CS Setup Time
tCSH
CS Hold Time
tCSD
CS Disable Time
tSU
Data Setup Time
tHD
Data Hold Time
tR tF tHI
CLK Rise Time CLK Fall Time Clock High Time
tLO
Clock Low Time
tCLD tV
Clock Delay Time Output Valid from Clock Low Output Hold Time Output Disable Time
tHO tDIS
tHS
HOLD Setup Time
tHH
HOLD Hold Time
tHZ
HOLD Low to Output High-Z
tHV
HOLD High to Output Valid
tWC --
Internal Write Cycle Time Endurance
Note 1: This parameter is periodically sampled and not 100% tested. 2: twc begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write cycle is complete. 3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS21146D-page 4
Preliminary
This document was created with FrameMaker 4 0 4
© 1996 Microchip Technology Inc.
25AA080/160
2.0 PRINCIPLES OF OPERATION
2.2 Read Status Register (RDSR)
The 25AA080/160 is an 1024/2048 byte EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular microcontroller families, including Microchip's midrange PIC16CXX microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with software. The 25AA080/160 contains an 8-bit instruction register. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. If the WPEN bit in the status register is set, the WP pin must be held high to allow writing to the non-volatile bits in the status register. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25AA080/160 in `HOLD' mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7 WPEN 654 XXX 3 BP1 2 BP0 1 WEL 0 WIP
The Write-In-Process (WIP) bit indicates whether the 25AA080/160 is busy with a write operation. When set to a `1' a write is in progress, when set to a `0' no write is in progress. This bit is read only. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a `1' the latch allows writes to the array and status register, when set to a `0' the latch prohibits writes to the array and status register. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the status register. This bit is read only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write protected. These bits are set by the user issuing the WRSR instruction. These bits are non-volatile. The Write Protect Enable (WPEN) bit is a non-volatile bit that is available as an enable bit for the WP pin. The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write protected, only writes to non-volatile bits in the status register are disabled. See Table 2-2 for matrix of functionality on the WPEN bit and Figure 2-1 for a flowchart of Table 2-2. See Figure 3-5 for RDSR timing sequence.
2.1
Write Enable (WREN) and Write Disable (WRDI)
The 25AA080/160 contains a write enable latch. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. The following is a list of conditions under which the write enable latch will be reset: · · · · Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed
© 1996 Microchip Technology Inc.
Preliminary
DS21146D-page 5
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