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Details, datasheet, quote on part number:24AA164T
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| Part: | 24AA164T |
| Category: | Memory |
| Description: | Note:this Product Has Become 'Obsolete' And is no Longer Offered as a Viable Device For Design |
| Company: | Microchip Technology, Inc. |
| Datasheet: | Download 24AA164T datasheet File size : 197 kB |
| Request For quote: | Find where to buy 24AA164T
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Datasheet text preview:
24AA164
16K 1.8V Cascadable I2CTM Serial EEPROM
FEATURES
· Single supply with operation down to 1.8V · Low power CMOS technology - 1 mA active current typical - 10 µA standby current typical at 5.5V - 5 µA standby current typical at 3.0V · Organized as 8 blocks of 256 bytes (8 x 256 x 8) · 2-wire serial interface bus, I2CTM compatible · Functional address inputs for cascading up to 8 devices · Schmitt trigger, filtered inputs for noise suppression · Output slope control to eliminate ground bounce · 100 kHz (1.8V) and 400 kHz (5V) compatibility · Self-timed write cycle (including auto-erase) · Page-write buffer for up to 16 bytes · 2 ms typical write cycle time for page-write · Hardware write protect for entire memory · Can be operated as a serial ROM · Factory programming (QTP) available · ESD protection > 4,000V · 1,000,000 Erase/Write cycles guaranteed · Data retention > 200 years · 8-pin DIP, 8-lead SOIC packages · Available for commercial temperature range - Commercial (C): 0°C to +70°C
PACKAGE TYPES
PDIP A0 A1 A2 VSS 1 24AA164 2 3 4 8 7 6 5 VCC WP SCL SDA
8-lead SOIC A0 A1 A2 VSS 1
24AA164
8 7 6 5
VCC WP SCL SDA
2 3 4
DESCRIPTION
The Microchip Technology Inc. 24AA164 is a cascadable 16K bit Electrically Erasable PROM. The device is organized as eight blocks of 256 x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 1.8 volts (end-of-life voltage for most popular battery technologies) with standby and active currents of only 5 µA and 1 mA respectively. The 24AA164 also has a page-write capability for up to 16 bytes of data. The 24AA164 is available in the standard 8-pin DIP and 8-lead surface mount SOIC packages. The three select pins, A0, A1, and A2, function as chip select inputs and allow up to eight devices to share a common bus, for up to 128K bits total system EEPROM.
BLOCK DIAGRAM
A0 A1 A2 WP HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY (8 x 256 x 8) PAGE LATCHES
SDA
SCL YDEC
VCC VSS
SENSE AMP R/W CONTROL
I2C is a trademark of Philips Corporation.
© 1999 Microchip Technology Inc.
DS21100F-page 1
24AA164
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name VSS SDA SCL WP VCC A0, A1, A2
PIN FUNCTION TABLE
Function Ground Serial Address/Data I/O Serial Clock Write Protect Input 1.8V to 6.0V Power Supply Chip Address Inputs
VCC..7.0V All inputs and outputs w.r.t. VSS ......... -0.3V to VCC +1.0V Storage temperature .... -65°C to +150°C Ambient temp. with power applied........ -65°C to +125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins ........ 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = 1.8V to +6.0 Commercial (C): Tamb = 0°C to +70°C Parameter Symbol Min Typ Max -- .3 VCC -- .40 10 10 10 -- 0.5 -- 0.05 -- -- 3 3 -- 1 -- 100 30 -- Units V V V V µA µA pF mA mA mA mA µA µA µA Conditions
WP, SCL and SDA pins: High level input voltage VIH .7 VCC Low level input voltage VIL -- Hysteresis of Schmitt trigger inputs VHYS .05 VCC -- Low level output voltage VOL Input leakage current ILI -10 Output leakage current ILO -10 Pin capacitance CIN, -- (all inputs/outputs COUT Operating current ICC Write -- -- ICC Read -- -- Standby current ICCS -- -- --
Note: This parameter is periodically sampled and not 100% tested.
(Note) IOL = 3.0 mA, VCC = 1.8V VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note 1) Tamb = 25°C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 1.8V, SCL = 100 kHz VCC = 5.5V, SCL = 400 kHz VCC = 1.8V, SCL = 100 kHz VCC = 5.5V, SDA = SCL=VCC VCC = 3.0V, SDA = SCL=VCC VCC = 1.8V, SDA = SCL=VCC WP = VSS
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL
TSU:STA THD:STA TSU:STO
SDA
START
STOP
DS21100F-page 2
© 1999 Microchip Technology Inc.
24AA164
TABLE 1-3: AC CHARACTERISTICS
STANDARD MODE Min Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- VCC = 4.5-5.5V FAST MODE Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3)
Parameter
Symbol
Units
Remarks
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition
Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance
TOF TSP TWR --
-- -- -- 1M
250 50 10 --
20 + 0.1 CB -- -- 1M
250 50 10 --
ns ns
ms Byte or Page mode cycles 25°C, Vcc = 5.0V, Block Mode ((Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS =specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2:
BUS TIMING DATA
TF THIGH TLOW TR
SCL TSU:STA THD:STA SDA IN TSP TAA SDA OUT TAA THD:DAT TSU:DAT TSU:STO
TBUF
© 1999 Microchip Technology Inc.
DS21100F-page 3
24AA164
2.0 FUNCTIONAL DESCRIPTION
3.4 Data Valid (D)
The 24AA164 supports aBi-directional two wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24AA164 works as slave. Both, master and slave can operate as transmitter or receiver but the master device determines which mode is activated. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: · Data transfer may be initiated only when the bus is not busy. · During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24AA164 does not generate any acknowledge bits if an internal programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24AA164) will leave the data line HIGH to enable the master to generate the STOP condition.
FIGURE 3-1:
(A) SCL
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B) (D) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
DS21100F-page 4
© 1999 Microchip Technology Inc.
24AA164
3.6 Device Addressing
4.0
4.1
WRITE OPERATION
Byte Write
A control byte is the first byte received following the star t condition from the master device. The first bit is always a one. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used to select which of the eight devices are to be accessed. The A1 bit must be the inverse of the A1 device select pin. The next three bits of the control byte are the block select bits (B2, B1, B0). They are used by the master device to select which of the eight 256 word blocks of memory are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Following the start condition, the 24AA164 looks for the slave address for the device selected. Depending on the state of the R/W bit, the 24AA164 will select a read or write operation. Operation Read Write Control Code 1 1 A2 A1 A0 A2 A1 A0 Block Select Block Address Block Address R/W 1 0
Following the start condition from the master, the device code (4 bits), the block address (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24AA164. After receiving another acknowledge signal from the 24AA164 the master device will transmit the data word to be written into the addressed memory location. The 24AA164 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24AA164 will not generate acknowledge signals (Figure 4-1).
4.2
Page Write
FIGURE 3-2:
START
CONTROL BYTE ALLOCATION
READ/WRITE SLAVE ADDRESS R/W A
1 MSB
A2
A1
A0
B2
B1
B0 LSB
The write control byte, word address and the first data byte are transmitted to the 24AA164 in the same way as in a byte write. But instead of generating a stop condition the master transmits up to 16 data bytes to the 24AA164 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remains constant. If the master should transmit more than 16 words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-2).
Note:
Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or Ôpage sizeÕ) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
© 1999 Microchip Technology Inc.
DS21100F-page 5
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