|
Details, datasheet, quote on part number:24AA256ISM
| |
Datasheet text preview:
M
Part Number 24AA256 24LC256
100
24AA256/24LC256
PACKAGE TYPE
PDIP
256K I2CTMCMOS Serial EEPROM
DEVICE SELECTION TABLE
VCC Range 1.8-5.5V 2.5-5.5V Max Clock Frequency 400 kHz 400 kHz Temp Ranges I I, E
A0 A1 A2 Vss
1
8
Vcc WP SCL SDA
24xx256
2 3 4
7 6 5
kHz for VCC < 2.5V. 100 kHz for E temperature range.
FEATURES
· Low power CMOS technology - Maximum write current 3 mA at 5.5V - Maximum read current 400 µA at 5.5V - Standby current 100 nA typical at 5.5V · 2-wire serial interface bus, I2C compatible · Cascadable for up to eight devices · Self-timed ERASE/WRITE cycle · 64-byte page-write mode available · 5 ms max write-cycle time · Hardware write protect for entire array · Schmitt trigger inputs for noise suppression · 100,000 erase/write cycles guaranteed · Electrostatic discharge protection > 4000V · Data retention > 200 years · 8-pin PDIP and SOIC (208 mil) packages · Temperature ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C
SOIC A0 A1 A2 VSS 1 8 VCC WP SCL SDA
24xx256
2 3 4
7 6 5
BLOCK DIAGRAM
A0...A2 WP
HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
DESCRIPTION
The Microchip Technology Inc. 24AA256/24LC256 (24xx256*) is a 32K x 8 (256K bit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.8V to 5.5V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device also has a page-write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 256K boundary. Functional address lines allow up to eight devices on the same bus, for up to 2 Mbit address space. This device is available in the standard 8-pin plastic DIP, and 8-pin SOIC (208 mil) packages.
I/O
SCL
YDEC
SDA VCC VSS
SENSE AMP R/W CONTROL
I2C is a trademark of Philips Corporation. *24xx256 is used in this document as a generic part number for the 24AA256/24LC256 devices.
© 1998 Microchip Technology Inc.
DS21203C-page 1
24AA256/24LC256
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1
Name VSS SDA SCL WP VCC
PIN FUNCTION TABLE
Function Ground Serial Data Serial Clock Write Protect Input +1.8 to 5.5V (24AA256) +2.5 to 5.5V (24LC256)
A0, A1, A2 User Configurable Chip Selects
VCC.......7.0V All inputs and outputs w.r.t. VSS ..... -0.6V to VCC +1.0V Storage temperature .........-65°C to +150°C Ambient temp. with power applied.......-65°C to +125°C Soldering temperature of leads (10 seconds) ... +300°C ESD protection on all pins ........ 4 kV *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2
DC CHARACTERISTICS
Industrial (I): VCC = +1.8V to 5.5V Automotive (E): VCC = +4.5V to 5.5V Symbol Min Max Tamb = -40°C to +85°C Tamb = -40°C to 125°C Units Conditions
All parameters apply across the specified operating ranges unless otherwise noted. Parameter A0, A1, A2, SCL, SDA, and WP pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current
VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS
0.7 VCC -- 0.05 VCC -- -10 -10 -- -- -- --
-- 0.3 VCC 0.2 VCC -- 0.40 10 10 10 3 400 1
V V V V V µA µA pF mA µA µA
Vcc 2.5V Vcc < 2.5V VCC 2.5V (Note) IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC VOUT = VSS or VCC VCC = 5.0V (Note) Tamb = 25°C, fc= 1 MHz VCC = 5.5V VCC = 5.5V, SCL = 400 kHz SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING DATA
TF THIGH VHYS TR
SCL
TSU:STA TLOW THD:DAT TSU:DAT TSU:STO
SDA IN
THD:STA TSP TAA TBUF
SDA OUT
WP
(protected) (unprotected)
TSU:WP
THD:WP
DS21203C-page 2
© 1998 Microchip Technology Inc.
24AA256/24LC256
TABLE 1-3 AC CHARACTERISTICS
Tamb = -40°C to +85°C Tamb = -40°C to 125°C
Conditions 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V (Note 1) 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V (Note 2) 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V 4.5V VCC 5.5V (E Temp range) 1.8V VCC 2.5V 2.5V VCC 5.5V CB 100 pF (Note 1) (Notes 1 and 3) All parameters apply across the spec- Industrial (I): VCC = +1.8V to 5.5V ified operating ranges unless otherAutomotive (E): VCC = +4.5V to 5.5V wise noted. Parameter Clock frequency Symbol FCLK Min -- -- -- 4000 4000 600 4700 4700 1300 -- -- -- -- 4000 4000 600 4700 4700 600 0 250 250 100 4000 4000 600 4000 4000 600 4700 4700 1300 -- -- -- 4700 4700 1300 10 -- -- 100,000 Max 100 100 400 -- -- -- -- -- -- 1000 1000 300 300 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3500 3500 900 -- -- -- 250 50 5 -- Units kHz
Clock high time
THIGH
ns
Clock low time
TLOW
ns
SDA and SCL rise time (Note 1) SDA and SCL fall time START condition hold time
TR
ns
TF THD:STA
ns ns
START condition setup time
TSU:STA
ns
Data input hold time Data input setup time
THD:DAT TSU:DAT
ns ns
STOP condition setup time
TSU:STO
ns
WP setup time
TSU:WP
ns
WP hold time
THD:WP
ns
Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance Note 1: 2: 3: 4:
TAA
ns
TBUF
ns
TOF TSP TWC
ns ns ms cycles
25°C, VCC = 5.0V, Block Mode (Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip's BBS or website.
© 1998 Microchip Technology Inc.
DS21203C-page 3
24AA256/24LC256
2.0
2.1
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined: · Data transfer may be initiated only when the bus is not busy. · During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 4-1).
The A0, A1, A2 inputs are used by the 24xx256 for multiple device operation. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight devices may be connected to the same bus by using different chip select bit combinations. If left unconnected, these inputs will be pulled down internally to VSS.
2.2
SDA Serial Data
4.1
Bus not Busy (A)
Both data and clock lines remain HIGH. This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an opendrain terminal, therefore, the SDA bus requires a pullup resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz) For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
4.3
Stop Data Transfer (C)
2.3
SCL Serial Clock
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must end with a STOP condition.
This input is used to synchronize the data transfer from and to the device.
4.4
Data Valid (D)
2.4
WP
This pin can be connected to either VSS, VCC or left floating. An internal pull-down on this pin will keep the device in the unprotected state if left floating. If tied to VSS or left floating, normal memory operation is enabled (read/write the entire memory 0000-7FFF). If tied to VCC, WRITE operations are inhibited. Read operations are not affected.
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.
3.0
FUNCTIONAL DESCRIPTION
The 24xx256 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions while the 24xx256 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24xx256 does not generate any acknowledge bits if an internal programming cycle is in progress.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24xx256) will leave the data line HIGH to enable the master to generate the STOP condition.
DS21203C-page 4
© 1998 Microchip Technology Inc.
24AA256/24LC256
FIGURE 4-1:
(A) SCL (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE
STOP CONDITION
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge Bit
SCL SDA
1
2
3
4
5
6
7
8
9
1
2
3
Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
© 1998 Microchip Technology Inc.
DS21203C-page 5
|
|
