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Details, datasheet, quote on part number:24AA32-SN
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Datasheet text preview:
24AA32
32K 1.8V I2CTM Smart Serial EEPROM
FEATURES
· Voltage operating range: 1.8V to 6.0V - Peak write current 3 mA at 6.0V - Maximum read current 150 µA at 6.0V - Standby current 1 µA typical · Industry standard two-wire bus protocol, I2CTM compatible - Including 100 kHz (1.8V) and 400 kHz (5V) modes · Self-timed ERASE and WRITE cycles · Power on/off data protection circuitry · Endurance: - 10,000,000 Erase/Write (E/W) cycles guaranteed for High Endurance Block - 1,000,000 E/W cycles guaranteed for Standard Endurance Block · 8 byte page, or byte modes available · 1 page x 8 line input cache (64 bytes) for fast write loads · Schmitt trigger, filtered inputs for noise suppression · Output slope control to eliminate ground bounce · 2 ms typical write cycle time, byte or page · Factory programming (QTP) available · Up to 8 devices may be connected to the same bus for up to 256K bits total memory · Electrostatic discharge protection > 4000V · Data retention > 200 years · 8-pin PDIP/SOIC packages · Temperature ranges - Commercial (C): 0°C to +70°C
PACKAGE TYPES
PDIP A0 A1 A2 VSS 1 2 3 4 24A A 32 8 7 6 5 VCC NC SCL SDA
SOIC 1 2 3 4
24AA32
A0 A1 A2 VSS
8 7 6 5
VCC NC SCL SDA
BLOCK DIAGRAM
A0..A2 HV GENERATOR
DESCRIPTION
The Microchip Technology Inc. 24AA32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM capable of operation across a broad voltage range (1.8V to 6.0V). This device has been developed for advanced, low power applications such as personal communications or data acquisition. The 24AA32 features an input cache for fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4K-bit block of ultrahigh endurance memory for data that changes frequently. The 24AA32 is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to 8 - 24AA32 devices on the same bus, for up to 256K bits address space. Advanced CMOS technology and broad voltage range make this device ideal for low-power/low voltage, nonvolatile code
I/O CONTROL LOGIC MEMORY CONTROL LOGIC EEPROM ARRAY XDEC PAGE LATCHES
I/O
SCL
Cache
SDA VCC VSS
YDEC
SENSE AMP R/W CONTROL
and data applications. The 24AA32 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC package.
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
DS21124C-page 1
This document was created with FrameMaker 4 0 4
24AA32
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name A0..A2 VSS SDA SCL VCC NC
PIN FUNCTION TABLE
Function User Configurable Chip Selects Ground Serial Address/Data I/O Serial Clock +1.8V to 6.0V Power Supply No Internal Connection
VCC ..........7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VCC +1.0V Storage temperature .... -65°C to +150°C Ambient temp. with power applied ....... -65°C to +125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins ........ 4 kV
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +1.8V to 6.0V Commercial (C): Tamb Industrial (I): Tamb Parameter Symbol Min Max Units = 0°C to +70°C = -40°C to +85°C Conditions
A0, A1, A2, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS .7 VCC -- .05 VCC -- -10 -10 -- -- -- -- -- .3 Vcc -- .40 10 10 10 3 150 5 2
Note: This parameter is periodically sampled and not 100% tested.
V V V V µA µA pF mA µA µA µA (Note) IOL = 3.0 mA VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V Note 1 Tamb = 25°C, Fclk = 1 MHz VCC = 6.0V, SCL = 400 kHz VCC = 6.0V, SCL = 400 kHz VCC = 5.0V, SCL = SDA = VCC (Note) VCC = 1.8V, SCL = SDA = VCC (Note)
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL
TSU:STA THD:STA TSU:STO
SDA
START
STOP
DS21124C-page 2
© 1996 Microchip Technology Inc.
24AA32
TABLE 1-3: AC CHARACTERISTICS
VCC = 1.8V-6.0V VCC = 4.5 - 6.0V STD. MODE FAST MODE Symbol Min
Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700
Parameter
Units
kHz ns ns ns ns ns ns ns ns ns ns ns
Remarks
Max
100 -- -- 1000 300 -- -- -- -- -- 3500 --
Min
-- 600 1300 -- -- 600 600 0 100 600 -- 1300
Max
400 -- -- 300 300 -- -- -- -- -- 900 --
(Note 1) (Note1) After this period the first clock pulse is generated Only relevant for repeated START condition
Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance High Endurance Block Rest of Array
TOF TSP TWR -- --
-- -- -- 10M 1M
250 50 5 -- --
20 +0.1 CB -- -- 10M 1M
250 50 5 -- --
ns ns
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3)
ms/page (Note 4) cycles 25°C, Vcc = 5.0V, Block Cycle Mode (Note 5)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write cache for total time. 5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
TF THIGH TLOW SCL TSU:STA THD:STA SDA IN TSP TAA SDA OUT TAA THD:DAT TSU:DAT TSU:STO
TR
TBUF
© 1996 Microchip Technology Inc.
DS21124C-page 3
24AA32
2.0 FUNCTIONAL DESCRIPTION
3.4 Data Valid (D)
The 24AA32 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24AA32 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: · Data transfer may be initiated only when the bus is not busy. · During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24AA32 does not generate any acknowledge bits if an internal programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24AA32) will leave the data line HIGH to enable the master to generate the STOP condition.
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 3-1:
(A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
SCL
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
DS21124C-page 4
© 1996 Microchip Technology Inc.
24AA32
3.6 Device Addressing FIGURE 3-2:
START
A control byte is the first byte received following the start condition from the master device. The control byte consists of a four bit control code; for the 24AA32 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 3-3). Because only A11...A0 are used, the upper four address bits must be zeros. The most significant bit of the most significant byte of the address is transferred first. Following the start condition, the 24AA32 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA32 will select a read or write operation.
CONTROL BYTE ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
Operation Read Write
Control Code 1010 1010
Device Select Device Address Device Address
R/W 1 0
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
ADDRESS BYTE 1
A 0 R/W A 11 A 10 A 9 A 8 A 7
CONTROL BYTE
A 2 A 1
ADDRESS BYTE 0
· · · · · · A 0
1
0
1
0
0
0
0
0
SLAVE ADDRESS
DEVICE SELECT BUS
© 1996 Microchip Technology Inc.
DS21124C-page 5
This document was created with FrameMaker 4 0 4
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