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Part: 24C32A-IP
Category:
Memory
-> ROM
-> EEPROM
Description: 32k 5.0v i 2 C o Serial EePROM
Company: Microchip Technology, Inc.
Datasheet: Download 24C32A-IP datasheet File size : 267 kB
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Datasheet text preview:
24C32A
32K 5.0V I2CTM Serial EEPROM
FEATURES
· Voltage operating range: 4.5V to 5.5V - Maximum write current 3 mA at 5.5V - Standby current 1 µA typical at 5.0V · 2-wire serial interface bus, I2CTM compatible · 100 kHz and 400 kHz compatibility · Self-timed ERASE and WRITE cycles · Power on/off data protection circuitry · Hardware write protect · 1,000,000 Erase/Write cycles guaranteed · 32-byte page or byte write modes available · Schmitt trigger filtered inputs for noise suppression · Output slope control to eliminate ground bounce · 2 ms typical write cycle time, byte or page · Up to eight devices may be connected to the same bus for up to 256K bits total memory · Electrostatic discharge protection > 4000V · Data retention > 200 years · 8-pin PDIP and SOIC packages · Temperature ranges - Commercial (C): 0°C to 70°C - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C
PACKAGE TYPES
PDIP A0 A1 A2 Vss 1 24C 32A 2 3 4 8 7 6 5 Vcc WP SCL SDA
SOIC
A0 A1 A2 Vss
1 24C32A 2 3 4
8 7 6 5
Vcc WP SCL SDA
DESCRIPTION
The Microchip Technology Inc. 24C32A is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. It has been developed for advanced, low power applications such as personal communications or data acquisition. The 24C32A also has a page-write capability of up to 32 bytes of data. The 24C32A is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24C32A devices on the same bus, for up to 256K bits address space. Advanced CMOS technology and broad voltage range make this device ideal for low-power/low-voltage, nonvolatile code and data applications. The 24C32A is available in the standard 8-pin plastic DIP and both 150 mil and 200 mil SOIC packaging.
BLOCK DIAGRAM
A0..W2 AP WP
HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
I/O
SCL
YDEC
SDA VCC VSS
SENSE AMP R/W CONTROL
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21163B-page 1
24C32A
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name A0..A2 VSS SDA SCL WP VCC
PIN FUNCTION TABLE
Function User Configurable Chip Selects Ground Serial Address/Data I/O Serial Clock Write Protect Input +4.5V to 5.5V Power Supply
VCC..7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VCC +1.0V Storage temperature .... -65°C to +150°C Ambient temp. with power applied ....... -65°C to +125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins ........ 4 kV
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Vcc = +4.5V to 5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Automotive(E): Tamb = -40°C to +125°C Parameter Symbol Min Typ Max A0, A1, A2, SCL , SDA and WP pins: High level input voltage VIH .7 VCC -- -- .3 Vcc Low level input voltage VIL Hysteresis of Schmitt Trigger VHYS .05 -- inputs VCC Low level output voltage VOL -- .40 -10 10 Input leakage current ILI Output leakage current ILO -10 10 Pin capacitance CIN, COUT -- 10 (all inputs/outputs) -- 3 Operating current ICC Write ICC Read -- 0.5 Standby current ICCS -- 1 5 Note: This parameter is periodically sampled and not 100% tested.
Units
Conditions
V V V V µA µA pF mA mA µA
(Note) IOL = 3.0 mA VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note) Tamb = 25°C, Fc = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SCL = 400 kHz SCL = SDA = VCC = 5.5V
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL TSU:STA SDA THD:STA TSU:STO
START
STOP
DS21163B-page 2
Preliminary
© 1996 Microchip Technology Inc.
24C32A
TABLE 1-3: AC CHARACTERISTICS
Vcc = 4.5-5.5 Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance Symbol Min FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF TOF TSP TWR -- -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 -- -- -- 1M Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- 250 50 5 -- kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms cycles 25°C, Vcc = 5.0V, Block Mode (Note 4) (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition Units Remarks
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
TF THIGH TLOW TR
SCL TSU:STA SDA IN THD:STA TSP TAA SDA OUT THD:STA THD:DAT TSU:DAT TSU:STO
TAA
TBUF
© 1996 Microchip Technology Inc.
Preliminary
DS21163B-page 3
24C32A
2.0 FUNCTIONAL DESCRIPTION
3.4 Data Valid (D)
The 24C32A supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C32A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: · Data transfer may be initiated only when the bus is not busy. · During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24C32A does not generate any acknowledge bits if an internal programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24C32A) will leave the data line HIGH to enable the master to generate the STOP condition.
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 3-1:
(A) SCL (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE
STOP CONDITION
DS21163B-page 4
Preliminary
© 1996 Microchip Technology Inc.
24C32A
3.6 Device Addressing
A control byte is the first byte received following the start condition from the master device. The control byte consists of a 4-bit control code; for the 24C32A this is set as 1010 binary for read and write (R/W) operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 3-3). Because only A11...A0 are used, the upper four address bits must be zeros. The most significant bit of the most significant byte of the address is transferred first. Following the start condition, the 24C32A monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24C32A will select a read or write operation. Operation Read Write Control Code 1010 1010 Device Select Device Address Device Address R/W 1 0
FIGURE 3-2:
CONTROL BYTE ALLOCATION
READ/WRITE
START
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
A 2 A 1 A 0 R/W
ADDRESS BYTE 1
A 11 A 10 A 9 A 8 A 7
ADDRESS BYTE 0
· · · · · · A 0
1
0
1
0
0
0
0
0
SLAVE ADDRESS
DEVICE SELECT BUS
© 1996 Microchip Technology Inc.
Preliminary
DS21163B-page 5
Others parts begin by 24
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