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Part: 24LC21A-ISN
Category:
Memory
-> ROM
-> EEPROM
Description: 1k 2.5v Dual Mode i 2 C Serial EePROM
Company: Microchip Technology, Inc.
Datasheet: Download 24LC21A-ISN datasheet File size : 137 kB
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Datasheet text preview:
24LC21A
1K 2.5V Dual Mode I2CTM Serial EEPROM
FEATURES
· Single supply with operation down to 2.5V · Completely implements DDC1TM/DDC2TM interface for monitor identification, including recovery to DDC1 · Pin and function compatible with 24LC21 · Low power CMOS technology - 1 mA typical active current - 10 µA standby current typical at 5.5V · 2-wire serial interface bus, I2CTM compatible · 100 kHz (2.5V) and 400 kHz (5V) compatibility · Self-timed write cycle (including auto-erase) · Page-write buffer for up to eight bytes · 10,000,000 erase/write cycles guaranteed · Data retention > 200 years · ESD Protection > 4000V · 8-pin PDIP and SOIC package · Available for extended temperature ranges - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C
PACKAGE TYPES
PDIP
NC NC NC VSS
SOIC
1 24LC 21A 2 3 4
8 7 6 5
VCC VCLK SCL SDA
NC NC NC VSS
1 24LC21A 2 3 4
8 7 6 5
VCC VCLK SCL SDA
DESCRIPTION
The Microchip Technology Inc. 24LC21A is a 128 x 8bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit-Only Mode and Bi-directional Mode. Upon power-up, the device will be in the Transmit-Only Mode, sending a serial bit stream of the memory array from 00h to 7Fh, clocked by the VCLK pin. A valid high to low transition on the SCL pin will cause the device to enter the transition mode, and look for a valid control byte on the I2C bus. If it detects a valid control byte from the master, it will switch into Bi-directional Mode, with byte selectable read/write capability of the memory array using SCL. If no control byte is received, the device will revert to the Transmit-Only Mode after it receives 128 consecutive VCLK pulses while the SCL pin is idle. The 24LC21A is available in a standard 8-pin PDIP and SOIC package in both commercial and industrial temperature ranges.
BLOCK DIAGRAM
HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
SDA
SCL YDEC
VCLK SENSE AMP R/W CONTROL
VCC VSS
DDC is a trademark of the Video Electronics Standards Association. I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21160B-page 1
24LC21A
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name VSS SDA SCL VCLK VCC NC
PIN FUNCTION TABLE
Function Ground Serial Address/Data I/O Serial Clock (Bi-directional Mode) Serial Clock (Transmit-Only Mode) +2.5V to 5.5V Power Supply No Connection
VCC ......7.0V All inputs and outputs w.r.t. VSS .... -0.6V to VCC +1.0V Storage temperature .. -65°C to +150°C Ambient temp. with power applied ..... -65°C to +125°C Soldering temperature of leads (10 seconds) .. +300°C ESD protection on all pins .... 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +2.5V to 5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb =-40°C to +85°C Parameter SCL and SDA pins: High level input voltage Low level input voltage Input levels on VCLK pin: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Note: Symbol VIH VIL VIH VIL VHYS VOL1 VOL2 ILI ILO Cin, Cout ICC Write ICC Read ICCS Min 0.7 VCC -- 2.0 -- .05 VCC -- -- -10 -10 -- -- -- -- -- Max -- 0.3 VCC -- 0.2 VCC -- 0.4 0.6 10 10 10 3 1 30 100 Units V V V V V V V µA µA pF mA mA µA µA VCC 2.7V (Note) VCC < 2.7V (Note) (Note) IOL = 3 mA, VCC = 2.5V (Note) IOL = 6 mA, VCC = 2.5V VIN = 0.1V to VCC VOUT = 0.1V to VCC VCC = 5.0V (Note) Tamb = 25°C, FCLK = 1 MHz VCC = 5.5V VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC Conditions
This parameter is periodically sampled and not 100% tested.
DS21160B-page 2
Preliminary
This document was created with FrameMaker 4 0 4
© 1996 Microchip Technology Inc.
24LC21A
TABLE 1-3: AC CHARACTERISTICS
Vcc= 2.5-5.5V Standard Mode Min Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time FCLK THIGH TLOW TR TF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc= 4.5 - 5.5V Fast Mode Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns
Parameter
Symbol
Units
Remarks
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)
START condition hold time THD:STA START condition setup time Data input hold time TSU:STA THD:DAT
Data input setup time TSU:DAT STOP condition setup time TSU:STO Output valid from clock TAA Bus free time TBUF
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) Byte or Page mode
Output fall time from VIH TOF minimum to VIL maximum Input filter spike suppresTSP sion (SDA and SCL pins) Write cycle time TWR Transmit-Only Mode Parameters Output valid from VCLK TVAA VCLK high time TVHIGH VCLK low time TVLOW VCLK setup time TVHST VCLK hold time TSPVL Mode transition time TVHZ Transmit-Only power up TVPU time Input filter spike suppresTSPV sion (VCLK pin) Endurance --
-- -- -- -- 4000 4700 0 4000 -- 0 -- 10M
250 50 10 2000 -- -- -- -- 1000 -- 100 --
20 + 0.1 CB -- -- -- 600 1300 0 600 -- 0 -- 10M
250 50 10 1000 -- -- -- -- 500 -- 100 --
ns ns ms ns ns ns ns ns ns ns ns cycles
25°C, Vcc = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
© 1996 Microchip Technology Inc.
Preliminary
DS21160B-page 3
24LC21A
2.0 FUNCTIONAL DESCRIPTION
The 24LC21A is designed to comply to the DDC Standard proposed by VESA (Figure 3-3) with the exception that it is not Access.bus capable. It operates in two modes, the Transmit-Only Mode and the Bi-directional Mode. There is a separate 2-wire protocol to support each mode, each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-Only Mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high to low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional Mode and look for its control byte to be sent by the master. If it detects its control byte, it will stay in the Bi-directional Mode. Otherwise, it will revert to the Transmit-Only Mode after it sees 128 VCLK pulses. mit-Only Mode (Section 2.2). In this mode, data is transmitted on the SDA pin in 8-bit bytes, with each byte followed by a ninth, null bit (Figure 2-1). The clock source for the Transmit-Only Mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted most significant bit first. Each byte within the memory array will be output in sequence. After address 7Fh in the memory array is transmitted, the internal address pointers will wrap around to the first memory location (00h) and continue. The Bi-directional Mode Clock (SCL) pin must be held high for the device to remain in the Transmit-Only Mode.
2.2
Initialization Procedure
2.1
Transmit-Only Mode
The device will power up in the Transmit-Only Mode at address 00H. This mode supports a unidirectional 2-wire protocol for continuous transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the Trans-
After VCC has stabilized, the device will be in the Transmit-Only Mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal sychronization. During this period, the SDA pin will be in a high impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit in address 00h. (Figure 2-2).
FIGURE 2-1:
TRANSMIT-ONLY MODE
SCL Tvaa SDA Bit 1 (LSB) Tvaa Null Bit Bit 1 (MSB) Bit 7
VCLK Tvhigh Tvlow
FIGURE 2-2:
DEVICE INITIALIZATION
Vcc SCL High Impedance for 9 clock cycles Tvpu VCLK 1 2 8 9 10 11 Tvaa Tvaa Bit 8 Bit 7
SDA
DS21160B-page 4
Preliminary
© 1996 Microchip Technology Inc.
24LC21A
3.0 BI-DIRECTIONAL MODE
Before the 24LC21A can be switched into the Bi-directional Mode (Figure 3-1), it must enter the transition mode, which is done by applying a valid high to low transition on the Bi-directional Mode Clock (SCL). As soon it enters the transition mode, it looks for a control byte 1010 000X on the I2CTM bus, and starts to count pulses on VCLK. Any high to low transition on the SCL line will reset the count. If it sees a pulse count of 128 on VCLK while the SCL line is idle, it will revert back to the Transmit-Only Mode, and transmit its contents starting with the most significant bit in address 00h. However, if it detects the control byte on the I2CTM bus, (Figure 3-2) it will switch to the in the Bi-directional Mode. Once the device has made the transition to the Bi-directional mode, the only way to switch the device back to the Transmit-Only Mode is to remove power from the device. The mode transition process is shown in detail in Figure 3-3. Once the device has switched into the Bi-directional Mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire Bi-directional data transmission protocol (I2CTM). In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bi-directional Mode Clock (SCL), controls access to the bus and generates the START and STOP conditions, while the 24LC21A acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. In the Bidirectional mode, the 24LC21A only responds to commands for device 1010 000X.
FIGURE 3-1:
MODE SCL
MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
Transmit Only Bi-directional TVHZ Recovery to Transmit-Only Mode
(MSB of data in 00h) SDA VCLK count = VCLK 1 2 3 4 127 128 Bit8
FIGURE 3-2:
SUCCESSFUL MODE TRANSITION TO BI-DIRECTIONAL MODE
Transition Mode with possibility to return to Transmit-Only Mode Bi-directional permanently
Transmit Only Mode MODE SCL SDA VCLK count = VCLK 1 2
n
S1 0
0
1
0
0
0
0
0
ACK
n < 128
© 1996 Microchip Technology Inc.
Preliminary
DS21160B-page 5
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