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Part: 24LC21T
Category:
Memory
-> ROM
-> EEPROM
-> Serial
-> I2C->128 to 1K
Description: Note:this Product Has Become 'Obsolete' And is no Longer Offered as a Viable Device For Design
Company: Microchip Technology, Inc.
Datasheet: Download 24LC21T datasheet File size : 733 kB
Request For quote: Find where to buy 24LC21T
Datasheet text preview:
24LC21
1K 2.5V Dual Mode I2CTM Serial EEPROM
FEATURES
· Single supply with operation down to 2.5V · Completely implements DDC1/DDC2 interface for monitor identification · Low power CMOS technology - 1 mA active current typical - 10 µA standby current typical at 5.5V · 2-wire serial interface bus, I2C compatible · Self-timed write cycle (including auto-erase) · Page-write buffer for up to 8 bytes · 100 kHz (2.5V) and 400 kHz (5V) compatibility · Factory programming (QTP) available · 1,000,000 erase/write cycles ensured · Data retention > 200 years · 8-pin PDIP and SOIC package · Available for extended temperature ranges - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C
PACKAGE TYPES
PDIP NC NC NC VSS 1 2 3 4 8 7 6 5 VCC VCLK SCL SDA
24LC21
SOIC 1 2 3 4 8 7 5 5
NC NC NC VSS
VCC VCLK SCL SDA
24LC21
DESCRIPTION
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit Only Mode and Bi-Directional Mode. Upon power-up, the device will be in the Transmit Only Mode, sending a serial bit stream of the entire memory array contents, clocked by the VCLK pin. A valid high to low transition on the SCL pin will cause the device to enter the Bi-Directional Mode, with byte selectable read/write capability of the memory array. The 24LC21 is available in a standard 8-pin PDIP and SOIC package in both commercial and industrial temperature ranges.
BLOCK DIAGRAM
VC L K HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
SDA
S CL YDEC
VCC VSS
SENSE AMP R/W CONTROL
DDC is a trademark of the Video Electronics Standards Association. I2C is a trademark of Philips Corporation.
2001 Microchip Technology Inc.
DS21095H- page 1
24LC21
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name VSS SDA SCL VCLK VCC NC
PIN FUNCTION TABLE
Function Ground Serial Address/Data I/O Serial Clock (Bi-Directional Mode) Serial Clock (Transmit-Only Mode) +2.5V to 5.5V Power Supply No Connection
VCC.. 7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VCC +1.0V Storage temperature .... -65°C to +150°C Ambient temp. with power applied ....... -65°C to +125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins ........ 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +2.5V to 5.5V Commercial (C): TAMB = 0°C to +70°C Industrial (I): TAMB = -40°C to +85°C Parameter Symbol VIH VIL VIH VIL VHYS VOL1 VOL2 ILI ILO CIN, COUT ICC Write ICC Read ICCS Min .7 VCC -- 2.0 -- .05 VCC -- -- -10 -10 -- -- -- -- -- Max -- .3 VCC .8 .2 VCC -- .4 .6 10 10 10 3 1 30 100 Units V V V V V V V µA µA pF mA mA µA µA -- -- VCC 2.7V (Note 1) VCC < 2.7V (Note 1) (Note 1) IOL = 3 mA, VCC = 2.5V (Note 1) IOL = 6 mA, VCC = 2.5V VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note1), TAMB = 25°C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC (Note 2) Conditions
SCL and SDA pins: High level input voltage Low level input voltage Input levels on VCLK pin: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current
Note 1: This parameter is periodically sampled and not 100% tested. 2: VLCK must be grounded.
DS2109 5H-page 2
2001 Microchip Technology Inc.
24LC21
TABLE 1-3: AC CHARACTERISTICS
Standard Mode Parameter Symbol Min Clock frequency FCLK Clock high time THIGH Clock low time TLOW SDA and SCL rise time TR SDA and SCL fall time TF START condition hold time THD:STA START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc= 4.5 - 5.5V Fast Mode Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns -- -- -- (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2) -- -- (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) Byte or Page mode -- -- -- -- -- 25°C, VCC = 5.0V, Block Mode (Note 4)
Units
Remarks
TOF Output fall time from VIH min to VIL max Input filter spike suppresTSP sion (SDA and SCL pins) Write cycle time TWR Transmit-Only Mode Parameters Output valid from VCLK TVAA VCLK high time TVHIGH VCLK low time TVLOW Mode transition time TVHZ Transmit-Only power up TVPU time Endurance --
-- -- -- -- 4000 4700 -- 0 1M
250 50 10 2000 -- -- 500 -- --
20 + .1 CB -- -- -- 600 1300 -- 0 1M
250 50 10 1000 -- -- 500 -- --
ns ns ms ns ns ns ns ns cycles
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website: www.microchip.com
2001 Microchip Technology Inc.
DS21095H- page 3
24LC21
2.0 FUNCTIONAL DESCRIPTION
The 24LC21 operates in two modes, the Transmit-Only Mode and the Bi-Directional Mode. There is a separate two wire protocol to support each mode, each having a separate clock input and sharing a common data line (SDA). The device enters the Transmit-Only Mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high to low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bi-Directional Mode. The only way to switch the device back to the Transmit-Only Mode is to remove power from the device. ninth, null bit (see Figure 2-1). The clock source for the Transmit-Only Mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted most significant bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. The Bi-Directional Mode Clock (SCL) pin must be held high for the device to remain in the Transmit-Only Mode.
2.2
Initialization Procedure
2.1
Transmit-Only Mode
The device will power up in the Transmit-Only Mode. This mode supports a unidirectional two wire protocol for transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the Transmit-Only Mode (see Initialization Procedure, below). In this mode, data is transmitted on the SDA pin in 8 bit bytes, each followed by a
After VCC has stabilized, the device will be in the Transmit-Only Mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a byte. The device will power up at an indeterminate byte address. (Figure 2-2).
FIGURE 2-1:
TRANSMIT ONLY MODE
S CL TVAA TVAA
SDA BIT 1 (LSB)
NULL BIT BIT 1 (MSB) B IT 7
V CLK TVHIGH TVLOW
FIGURE 2-2:
DEVICE INITIALIZATION
VCC S CL
TVAA
TVAA
S DA
HIGH IMPEDANCE FOR 9 CLOCK CYCLES TVPU
B IT 8
B IT 7
VC LK
1
2
8
9
10
11
DS2109 5H-page 4
2001 Microchip Technology Inc.
24LC21
3.0 BI-DIRECTIONAL MODE
3.1
The 24LC21 can be switched into the Bi-Directional Mode (see Figure 3-1) by applying a valid high to low transition on the Bi-Directional Mode Clock (SCL). When the device has been switched into the Bi-Directional Mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two wire bi-directional data transmission protocol. In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bi-Directional Mode Clock (SCL), controls access to the bus and generates the START and STOP conditions, while the 24LC21 acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
Bi-Directional Mode Bus Characteristics
The following bus protocol has been defined: · Data transfer may be initiated only when the bus is not busy. · During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (see Figure 3-2). 3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain HIGH. 3.1.2 START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.1.3 STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 3-1:
SCL
MODE TRANSITION
Transmit Only Mode Bi-Directional Mode
TVHZ
S DA
V CLK
FIGURE 3-2:
(A) SCL
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B) (D) (D) (C) (A)
S DA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
2001 Microchip Technology Inc.
DS21095H- page 5
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