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Part: 24LC256
Category:
Memory
-> ROM
-> EEPROM
-> Serial
-> I2C->64K to 512K
Description: The 24LC256 is a 32K X 8 (256K-bit) Serial Electrically Erasable Prom Memory With an I2C™ Compatible 2-wire Serial Interface Bus
Company: Microchip Technology, Inc.
Datasheet: Download 24LC256 datasheet File size : 733 kB
Request For quote: Find where to buy 24LC256
Datasheet text preview:
M
Features
24AA256/24LC256/24FC256
Description
The Microchip Technology Inc. 24AA256/24LC256/ 24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.8 V to 5.5 V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device also has a page-write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 256K boundary. Functional address lines allow up to eight devices on the same bus, for up to 2 M bit address space. This device is available in the standard 8-pin plastic DIP, SOIC, TSSOP, MSOP, DFN and 14-lead TSSOP packages.
256K I2CTM CMOS Serial EEPROM
· Low power CMOS technology - Maxim um write current 3 mA at 5.5 V - Maxim um read current 400 µA at 5.5 V - Standby current 100 nA typical at 5.5 V · 2-wire serial interface bus, I2C compatible · Cascadable for up to eight devices · Self-tim ed ERASE/WRITE cycle · 64-byte page-write mode available · 5 ms max write-cycle time · Hardware write protect for entire array · Output slope control to eliminate ground bounce · Schmitt trigger inputs for noise suppression · 1,000,000 erase/write cycles · Electrostatic discharge protection > 4000 V · Data retention > 200 years · 8-pin PDIP, SOIC, TSSOP, MSOP, and DFN packages · 14-lead TSSOP package · Tem perature ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C
Block Diagram
A0 A1 A2WP HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
I/O
Device Selection Table
S DA
SCL YDEC
Part Number 24AA256 24LC 256 24FC256
VCC Range 1.8-5.5 V 2.5-5.5 V 2.5-5.5 V
Max. Clock Frequency 400 kHz
(1 )
Temp. Ranges I I, E I
V CC VSS SENSE AMP R/W CONTROL
400 kHz 1 MH z
Note 1: 100 kHz for VCC < 2.5 V.
Package Types
PDIP/SOIC A0 A1 A2 VSS 1 24XX256 2 3 4 8 7 6 5 V CC WP SCL SDA A0 A1 A2 VSS TSSOP/MSOP * 1 24XX256 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 NC NC NC A2 VSS 1 2 3 4 5 6 7 TSSOP 14 13 12 11 10 9 8 VCC WP NC NC NC SCL SDA A0 A1 A2 VSS 1 2 4XX256 2 3 4 DF N 8 V CC 7 WP 6 SCL 5 SDA
* Pins A0 and A1 are no connects for the MSOP package only.
*24 XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
24XX256
2002 Microchip Technology Inc.
Preliminary
DS21203J-page 1
24AA256/24LC256/24FC256
1 .0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
VCC ..........6.5 V All inputs and outputs w.r.t. VSS ............. -0.6 V to VCC +1.0 V Storage temperature ............. -65°C to +150°C Ambient temp. with power applied .......... -65°C to +125°C ESD protection on all pins ............ 4 kV NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
1.1
24AA256/24LC256/24FC256 DC Electrical Specifications
Electrical Characteristics: Industrial (I): VCC = +1.8 V to 5.5 V Automotive (E): VCC = +2.5 V to 5.5 V Characteristic A0, A1, A2, SCL, SDA and WP pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Mi n -- 0.7 VCC -- 0.05 VCC Ma x -- -- 0.3 VCC 0.2 VCC -- Units -- V V V V -- -- VCC 2.5 V VCC < 2.5 V VCC 2.5 V (Note) TAMB = -40°C to +85°C TAMB = -40°C to +125°C Conditions
DC Specifications Param. No. D1 D2 D3 D4
Sym -- VIH VIL VHYS
D5 D6 D7 D8 D9 D10
VOL ILI ILO CIN, COUT ICC Write ICCS
-- -- -- -- -- -- --
0.40 ±10 ±10 10 400 3 1
V µA µA pF µA mA µA
IOL = 3.0 ma @ VCC = 4.5 V IOL = 2.1 ma @ VCC = 2.5 V VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC VOUT = VSS or VCC VCC = 5.0 V (Note) TAMB = 25°C, fC = 1 MHz VCC = 5.5 V, SCL = 400 kHz VCC = 5.5 V TAMB = -40°C to +85°C SCL = SDA = VCC = 5.5 V A0, A1, A2, WP = VSS TAMB = -40°C to +125°C SCL = SDA = VCC = 5.5 V A0, A1, A2, WP = VSS
ICC Read Operating current Standby current
--
5
µA
Note:
This parameter is periodically sampled and not 100% tested.
DS 21203J-page 2
Preliminary
2002 Microchip Technology Inc.
24AA256/24LC256/24FC256
1.2 24AA256/24LC256/24FC256 AC Electrical Specifications
Electrical Characteristics: Industrial (I): VC C = +1.8 V to 5.5 V Automotive (E): VC C = +2.5 V to 5.5 V Characteristic Clock frequency Min -- -- -- 4000 600 500 4700 1300 500 -- -- -- -- -- 4000 600 250 4700 600 250 0 250 100 100 4000 600 250 4000 600 600 4700 1300 1300 -- -- -- 4700 1300 500 10 + 0.1CB Max 100 400 1000 -- -- -- -- -- -- 1000 300 300 300 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3500 900 400 -- -- -- 250 250 50 5 -- Units k Hz TAM B = -40°C to +85°C TAM B = -40°C to +125°C Conditions 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 All except, 24FC256 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 (Note 2) 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 2.5 V VCC 5.5 V 24FC256 All except, 24FC256 (Note 1) 24FC256 (Note 1) All except, 24FC256 (Notes 1 and 3) -- 25°C (Note 4)
AC Specifications
Param. No. S ym FCLK
1
2
THIGH
Clock high time
ns
3
TLOW
Clock low time
ns
4
TR
SDA and SCL rise time (Note 1)
ns
5 6
TF
SDA and SCL fall time (Note 1)
ns ns
THD :STA START condition hold time
7
TSU:STA START condition setup time
ns
8 9
TH D:DAT Data input hold time TSU:DAT Data input setup time
ns ns
10
TSU :STO STOP condition setup time
ns
11
TSU:WP WP setup time
ns
12
THD:WP WP hold time
ns
13
TAA
Output valid from clock (Note 2)
ns
14
TBUF
Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum CB 100 pF Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance
ns
15
TOF
ns
16 17 18
No t e
TSP TWC --
-- -- 1,000,000
ns ms cycles
1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total End ura nce Model, which can be obtained on Microchip's website: www.microchip.com.
2002 Microchip Technology Inc.
Preliminary
DS21203J-page 3
24AA256/24LC256/24FC256
FIGURE 1-1: BUS TIMING DATA
5 2 D4 4
SCL SDA IN
7 6 16
3
8
9
10
13 SDA OUT (protected) (unprotected)
14
WP
11
12
DS 21203J-page 4
Preliminary
2002 Microchip Technology Inc.
24AA256/24LC256/24FC256
2 .0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
N am e A0 A1 (NC ) A2 VSS SDA SCL (NC ) WP VCC
PIN FUNCTION TABLE
8-pin PDIP 1 2 -- 3 4 5 6 -- 7 8 8-pin SOIC 1 2 -- 3 4 5 6 -- 7 8 8-pin TSSOP 1 2 -- 3 4 5 6 -- 7 8 14-pin TSSOP 1 2 3, 4, 5 6 7 8 9 10, 11, 12 13 14 8-pin MSOP -- -- 1, 2 3 4 5 6 -- 7 8 8-pin D FN 1 2 -- 3 4 5 6 -- 7 8 Function User Configurable Chip Select User Configurable Chip Select Not Connected User Configurable Chip Select Ground Serial Data Serial Clock Not Connected Write Protect Input +1.8 V to 5.5 V (24AA256) +2.5 V to 5.5 V (24LC256) +2.5 V to 5.5 V (24FC256)
2.1
A0, A1, A2 Chip Address Inputs
2.3
Serial Clock (SCL)
The A0, A1 and A2 inputs are used by the 24XX256 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. For the MSOP package only, pins A0 and A1 are not connected. Up to eight devices (two for the MSOP package) may be connected to the same bus by using different chip select bit combinations. If these pins are left unconnected, the inputs will be pulled down internally to VSS. If they are tied to VCC or driven high, the internal pulldown circuitry is disabled. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic `0' or logic `1'. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic `0' or logic `1' before normal device operation can proceed.
This input is used to synchronize the data transfer to and from the device.
2.4
Write Protect (WP)
This pin can be connected to either VSS, VCC or left floating. Internal pull-down circuitry on this pin will keep the device in the unprotected state if left floating. If tied to VSS or left floating, normal memory operation is enabled (read/write the entire memory 0000-7FFF). If tied to VCC, WRITE operations are inhibited. Read operations are not affected.
3 .0
FUNCTIONAL DESCRIPTION
2.2
Serial Data (SDA)
This is a bi-directional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
The 24XX256 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions while the 24XX256 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated.
2002 Microchip Technology Inc.
Preliminary
DS21203J-page 5
Others parts begin by 24
24-1 24-2 24-3 24-4 24-5 24-6
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