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Part: 24LC320-SN
Category:
Logic
-> Bus Exchangers
Description: 32k 2.5v Spi Bus Serial EePROM
Company: Microchip Technology, Inc.
Datasheet: Download 24LC320-SN datasheet File size : 733 kB
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Datasheet text preview:
25LC320
32K 2.5V SPITM Bus Serial EEPROM
FEATURES
· SPI modes 0,0 and 1,1 · 3.0 MHz Clock Rate · Single supply with Programming Operation down to 2.5V · Low Power CMOS Technology - Max Write Current: 5.0 mA - Read Current: 1 mA at 5.5V, 3 Mhz - Standby Current: 1 µA typical · 4096 x 8 Organization · 32-Byte Page · Sequential Read · Self-timed ERASE and WRITE Cycles · Block Write Protection - Protect none, 1/4, 1/2, or all of Array · Built-in Write Protection - Power On/Off Data Protection Circuitry - Write Enable Latch - Write Protect Pin · High Reliability - Endurance: 1M cycles (guaranteed) - Data Retention: >200 years - ESD protection: >4000V · 8-pin PDIP/SOIC, 14-pin TSSOP · Temperature ranges supported - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C
PACKAGE TYPES
DIP/SOIC CS SO WP VSS TSSOP
CS 1 SO 2 NC 3 NC 4 NC 5 WP 6 VSS 7 14 VCC 13 HOLD 12 NC 11 NC 10 NC 9 SCK 8 SI
1 25LC 320 25LC320 2 3 4
8 7 6 5
VCC HOLD SCK SI
BLOCK DIAGRAM
Status Register HV Generator
EEPROM I/O Control Logic Memory Control Logic X Dec Page Latches WP SI SO CS SCK HOLD Sense Amp. R/W Control Y Decoder Array
DESCRIPTION
The Microchip Technology Inc. 25LC320 is a 32K-bit serial Electrically Erasable PROM (EEPROM). The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. There are two other inputs that provide the end user with additional flexibility. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with exception of chip select, allowing the host to service higher priority interrupts. Also write operations to the Status Register can be disabled via the write protect pin (WP).
Vcc Vss
SPI is a trademark of Motorola.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21158B-page 1
25LC320
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
FIGURE 1-1: AC TEST CIRCUIT
Vcc 2.25 K
VCC ...... 7.0V All inputs and outputs w.r.t. VSS ....... -0.6V to VCC+1.0V Storage temperature .... -65°C to 150°C Ambient temperature under bias.......... -65°C to 125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins.... 4 kV
*Notice: Stresses above those listed under `Maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended period of time may affect device reliability
SO 1.8 K 100 pF
1.2
AC Test Conditions
TABLE 1-1:
Name CS SO SI SCK WP VSS VCC HOLD NC
PIN FUNCTION TABLE
Function Chip Select Input Serial Data Output Serial Data Input Serial Clock Input Write Protect Pin Ground Supply Voltage Hold Input No Connect
AC Waveform: VLO = 0.2V VHI = Vcc - 0.2V VHI = 4.0V
(Note 1) (Note 2)
Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC 4.0V 2: For VCC > 4.0V
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted: VCC = 2.5V to 5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Parameter High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Internal Capacitance (all inputs and outputs) Operating Current Symbol VIH1 VIH2 VIL1 VIL2 VOL VOH ILI ILO CINT ICC write Min 2.0 0.7 VCC -0.3 -0.3 -- VCC-0.5 -10 -10 -- -- -- -- -- -- Max VCC+1 VCC+1 0.8 0.3 VCC 0.4 -- 10 10 7 Units V V V V V V µA µA pF Test Conditions VCC 2.7V VCC< 2.7V VCC 2.7V VCC< 2.7V IOL=2.1 mA IOH=-400 µA CS=VIH, VIN=GND to VCC CS=VIH, VOUT=GND to VCC Tamb=25°C, FCLK= 1.0 MHz, VCC=5.5V (Note) VCC=5.5V; SO=Open VCC=2.5V; SO=Open VCC=5.5V; SO=Open, FCLK=3.0 MHz VCC=2.5V; SO=Open, FCLK=2.0 MHz CS=VCC=5.5V; VIN=Gnd or VCC CS=VCC=2.5V; VIN=Gnd or VCC
5 mA 3 mA ICC read 1 mA 500 µA µA Standby Current ICCS 5 2 µA Note: This parameter is periodically sampled and not 100% tested.
DS21158B-page 2
Preliminary
© 1996 Microchip Technology Inc.
25LC320
FIGURE 1-2: SERIAL INPUT TIMING
tCSD CS tCSS SCK tSU SI msb in tHD lsb in tR tCLD tF tCSH
SO
high impedance
FIGURE 1-3: SERIAL OUTPUT TIMING
CS tHI SCK tV SO msb out tHO tDIS lsb out tLO tCSH
SI
don't care
FIGURE 1-4: HOLD TIMING
CS tHS SCK tHZ SO n+2 n+1 n high impedance tHV n tSU n n-1 n-1 tHH tHS tHH
don't care SI HOLD n+2 n+1 n
© 1996 Microchip Technology Inc.
Preliminary
DS21158B-page 3
25LC320
TABLE 1-3: AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted: VCC = 2.5V to 5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Symbol fSCK tCSS tCSH tCSD tSU tHD tR tF tHI tLO tCLD tV tHO tDIS tHS tHH tHZ tHV tWC -- Parameter Clock Frequency CS Setup Time CS Hold Time CS Disable Time Data Setup Time Data Hold Time CLK Rise Time CLK Fall Time Clock High Time Clock Low Time Clock Delay Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD Setup Time HOLD Hold Time HOLD Low to Output High-Z HOLD High to Output Valid Internal Write Cycle Time Endurance Min -- -- 100 250 100 250 250 500 30 50 50 100 -- -- 150 250 150 250 50 -- -- 0 -- -- 100 100 100 100 100 150 100 150 -- 1M Max 3 2 -- -- -- -- -- -- -- -- -- -- 2 2 -- -- -- -- -- 150 250 -- 200 250 -- -- -- -- -- -- -- -- 5 -- Units MHz MHz ns ns ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V (Note 1) (Note 1) VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V (Note 1) VCC=2.5V to 4.5V (Note 1) VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V VCC=2.5V to 4.5V VCC=4.5V to 5.5V (Note 1) VCC=2.5V to 4.5V (Note 1)
VCC=4.5V to 5.5V (Note 1) VCC=2.5V to 4.5V (Note 1) ms (Note 2) E/W Cycles 25°C, Vcc = 5.0V, Block Mode (Note 3)
Note 1: This parameter is periodically sampled and not 100% tested. 2: tWC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write cycle is complete. 3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS21158B-page 4
Preliminary
© 1996 Microchip Technology Inc.
25LC320
2.0 PRINCIPLES OF OPERATION
2.2 Read Status Register (RDSR)
The 25LC320 is a 4096 byte EEPROM designed to interface directly with the serial peripheral interface (SPITM ) port of many of today's popular microcontroller families, including Microchip's midrange PIC16CXX microcontrollers. It may also interface with microcontrollers that do not have a built-in SPITM port by using discrete I/O lines programmed properly with software. The 25LC320 contains an 8-bit instruction register. The par t is accessed via the SI pin, with data being clocked in on the rising edge of SCK. If the WPEN bit in the Status Register is set, the WP pin must be held high to allow writing to the non-volatile bits in the status register. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPITM bus, the user can assert the HOLD input and place the 25LC320 in `HOLD' mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7 WPEN 654 XXX 3 BP1 2 BP0 1 WEL 0 WIP
The Write-In-Process (WIP) bit indicates whether the 25LC320 is busy with a write operation. When set to a `1' a write is in progress, when set to a `0' no write is in progress. This bit is read only. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a `1' the latch allows writes to the array and status register, when set to a `0' the latch prohibits writes to the array and status register. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the status register. This bit is read only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write protected. These bits are set by the user issuing the WRSR instruction. These bits are non-volatile. The Write Protect Enable (WPEN) bit is a non-volatile bit that is available as an enable bit for the WP pin. The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write protected, only writes to non-volatile bits in the status register are disabled. See Table 2-2 for matrix of functionality on the WPEN bit and Figure 2-1 for a flowchar t of Table 2-2. See Figure 3-5 for RDSR timing sequence.
2.1
Write Enable (WREN) and Write Disable (WRDI)
The 25LC320 contains a write enable latch. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. The following is a list of conditions under which the write enable latch will be reset: · · · · Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed
TABLE 2-1:
INSTRUCTION SET
Description Set the write enable latch (enable write operations) Reset the write enable latch (disable write operations) Read status register Write status register (write protect enable and block write protection bits) Read data from memory array beginning at selected address Write data to memory array beginning at selected address
Instruction Name Instruction Format WREN WRDI RDSR WRSR READ WRITE 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
TABLE 2-2:
WPEN 0 0 1 1 X X
WRITE PROTECT FUNCTIONALITY MATRIX
WP X X Low Low High High WEL 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable
© 1996 Microchip Technology Inc.
Preliminary
DS21158B-page 5
Others parts begin by 24
24-1 24-2 24-3 24-4 24-5 24-6
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