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Details, datasheet, quote on part number:27C17AT-25ITS
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Datasheet text preview:
28C17A
16K (2K x 8) CMOS EEPROM
FEATURES
· Fast Read Access Time--150 ns · CMOS Technology for Low Power Dissipation - 30 mA Active - 100 µA Standby · Fast Byte Write Time--200 µs or 1 ms · Data Retention >200 years · High Endurance - Minimum 104 Erase/Write Cycles · Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches · Data Polling; Ready/Busy · Chip Clear Operation · Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit · Electronic Signature for Device Identification · 5-Volt-Only Operation · Organized 2Kx8 JEDEC Standard Pinout - 28 Pin Dual-In-Line Package - 32-Pin PLCC Package - 28-Pin Thin Small Outline Package (TSOP) 8x20mm - 28-Pin Very Small Outline Package (VSOP) 8x13.4mm · Available for Extended Temperature Ranges: - Commercial: 0°C to +70°C - Industrial: -40°C to +85°C
PACKAGE TYPES
RDY/BN Y S AC A7 A6 A5 A4 A3 A2 A1 I0 I/O0 I/O1 /V 2 O
SS
·1 3 2 4 5 6 7 8 9 1 10 11 12 13 4
28 2 27 26 25 24 23 22 21 10 19 18 17 16 5
Vcc N WE AC A8 A6 N9 A5 OC A4 A3 AE C10 A2 A1 IE N0 I/O7 IC I/O6 /O0 I/O5 I/O4 /O3
1 NDY /B S Y
32 W c c 31 N E
3N 4 A7 2 RC
VU
3
0 29 A8 28 N9 27 NC 26 OC 25 A E 24 C10 23 I E 22 I/O7 1
6 5 7 8 9 1 10 11 12 3 14 15 16 17 18 29 0
C /O6
· Pin 1 indicator on PLCC on top of package
OE N AC A9 N8 WC VE cc R DY/BN Y S AC A7 A6 A5 A4 3 9 1 10 11 12 13 4
OE N AC A9 8 WC N VE
CC
I/O1 V2 /O Ns s IU I/O3 I/O4 /O5
DIP/SOIC
P LC C
2 1 3 4 5 6 7 8
28 27 26 25 24 23 22 21 10 19 18 17 16 5
21 10 9 18 7 16 5 14 13 2 11 9 0 8 C A10 E I/O7 /O6 A I/O5 I/O4 /O3 VSS I/O2 I/O1 /O0 A0 1 A2
C A10 IE I/07 I/06 I/05 I/04 V03 / I ss I/02 I/01 A00 / A0 A1 2
TSOP
RDY/BSY NC A 7 A6 5 A4 3
22 23 4 25 26 27 8 2 1 3 4 5 7 6
VSOP
DESCRIPTION
The Microchip Technology Inc. 28C17A is a CMOS 16K nonvolatile electrically Erasable PROM. The 28C17A is accessed like a static RAM for the read or write cycles without the need of external components. During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wiredor systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications.
BLOCK DIAGRAM
I/O0 I/O7
VSS VCC
CE
OE WE
B dy/ R usy
Data Protection Circuitry Chip Enable/ Output Enable Control Logic
Auto Erase/Write Timing
Data P oll
Input/Output B uffers
Program Voltage Generation
A0
a L t c h e s
DY ecoder
Y Gating
DX ecoder
16K bit Cell Matrix
A10
© 1996 Microchip Technology Inc.
DS11127G-page 1
This document was created with FrameMaker 4 0 4
28C17A
1.0
1.1
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS*
TABLE 1-1:
Name A0 - A10 CE OE WE I/O0 - I/O7 RDY/Busy VCC VSS NC NU
PIN FUNCTION TABLE
Function Address Inputs Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy +5V Power Supply Ground No Connect; No Internal Connection Not Used; No External Connection is Allowed
VCC and input voltages w.r.t. VSS ....... -0.6V to + 6.25V Voltage on OE w.r.t. VSS ............ -0.6V to +13.5V Voltage on A9 w.r.t. VSS .... -0.6V to +13.5V Output Voltage w.r.t. VSS ....... -0.6V to VCC+0.6V Storage temperature .. -65°C to +125°C Ambient temp. with power applied ....... -50°C to +95°C
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
VCC = +5V ±10% Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C
Parameter Input Voltages Input Leakage Input Capacitance Output Voltages Output Leakage Output Capacitance Power Supply Current, Active Power Supply Current, Standby
Status Logic `1' Logic `0' -- -- Logic `1' Logic `0' -- -- TTL input
Symbol VIH VIL ILI CIN VOH VOL ILO COUT ICC
Min 2.0 -0.1 -10 -- 2.4
Max Vcc+1 0.8 10 10
Units V V µA pF V V µA pF mA mA mA µA
Conditions
VIN = -0.1V to Vcc +1 VIN = 0V; Tamb = 25°C; f = 1 MHz IOH = -400 µA IOL = 2.1 mA VOUT = -0.1V to VCC +0.1V VIN = 0V; Tamb = 25°C; f = 1 MHz f = 5 MHz (Note 1) VCC = 5.5V; CE = VIH (0°C to +70°C) CE = VIH (-40°C to +85°C) CE = VCC-0.3 to Vcc +1
0.45 -10 -- -- -- 10 12 30 2 3 100
ICC(S)TTL TTL input TTL input ICC(S)TTL CMOS input ICC(S)CMOS
Note 1: AC power supply current above 5MHz: 1mA/MHz.
DS11127G-page 2
© 1996 Microchip Technology Inc.
28C17A
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature:
28C17A-15
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C
28C17A-20 28C17A-25
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE High to Output Float Output Hold from Address, CE or OE, whichever occurs first. Endurance
Symbol Min tACC tCE tOE tOFF tOH -- -- -- 0 0 Max 150 150 70 50 -- Min -- -- -- 0 0 Max 200 200 80 55 -- Min -- -- -- 0 0 Max 250 250 100 70 --
Units ns ns ns ns ns
Conditions OE = CE = VIL OE = VIL CE = VIL
--
1M
--
1M
--
1M
--
cycles
25°C, Vcc = 5.0V, Block Mode (Note)
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
VIH Address VIL VIH CE VIL
READ WAVEFORMS
Address Valid
t CE(2)
VIH OE VIL VOH Data VOL t ACC VIH WE VOL t OE(2) High Z t OFF(1,3) t OH Valid Output High Z
Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested
© 1996 Microchip Technology Inc.
DS11127G-page 3
28C17A
TABLE 1-4: BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise/Fall Times: Ambient Temperature: Parameter Address Set-Up Time Address Hold Time Data Set-Up Time Data Hold Time Write Pulse Width Write Pulse High Time OE Hold Time OE Set-Up Time Data Valid Time Time to Device Busy Write Cycle Time (28C17A) Write Cycle Time (28C17AF) Symbol tAS tAH tDS tDH tWPL tWPH tOEH tOES tDV tDB tWC tWC Min 10 50 50 10 100 50 10 10 -- 2 -- -- VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Max -- -- -- -- -- -- -- -- 1000 50 1 200 Units ns ns ns ns ns ns ns ns ns ns ms µs 0.5 ms typical 100 µs typical Note 2 Note 1 Remarks
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the positive edge of CE or WE, whichever occurs first 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2:
PROGRAMMING WAVEFORMS
VIH
Address VIL VIH CE, WE VIL t DV Data In VIH VIL t OES VIH OE VIL t OEH VOH Rdy/Busy VOL t WC t DB Busy Ready t DS t AS t AH t WPL t DH
DS11127G-page 4
© 1996 Microchip Technology Inc.
28C17A
FIGURE 1-3:
VIH
Address VIL Address Valid t ACC t CE t WPH
DATA POLLING WAVEFORMS
Last Written Address Valid
VIH
CE VIL
VIH
WE VIL
t WPL t OE
VIH
OE VIL
t DV VIH
Data VIL Data In Valid t WC I/O7 Out True Data Out
FIGURE 1-4:
VIH CE VIL VH OE VIH VIH WE VIL
CHIP CLEAR WAVEFORMS
tS
tW
tH
tW = 10ms tS = tH = 1µs VH = 12.0V ±0.5V
TABLE 1-5:
Mode Chip Clear Extra Row Read Extra Row Write
SUPPLEMENTARY CONTROL
CE VIL VIL * OE VH VIL VIH WE VIL VIH * A9 X A9 = VH A9 = VH Vcc VCC VCC VCC Data Out Data In I/OI
Note 1: VH = 12.0V ±0.5V
* Pulsed per programming waveforms.
© 1996 Microchip Technology Inc.
DS11127G-page 5
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