|
|
Part: 27LV256-25IL
Category:
Memory
-> EPROM
-> 8 Mb
Description: 256k ( 32k X 8 ) Low-voltage CMOS EPROM
Company: Microchip Technology, Inc.
Datasheet: Download 27LV256-25IL datasheet File size : 287 kB
Request For quote: Find where to buy 27LV256-25IL
Datasheet text preview:
27LV256
256K (32K x 8) Low-Voltage CMOS EPROM
FEATURES
· Wide voltage range 3.0V to 5.5V · High speed performance - 200 ns access time available at 3.0V · CMOS Technology for low power consumption - 8 mA Active current at 3.0V - 20 mA Active current at 5.5V - 100 µA Standby current · Factory programming available · Auto-insertion-compatible plastic packages · Auto ID aids automated programming · Separate chip enable and output enable controls · High speed "Express" programming algorithm · Organized 32K x 8: JEDEC standard pinouts - 28-pin Dual-in-line package - 32-pin PLCC package - 28-pin SOIC package - 28-pin VSOP package - Tape and reel · Data Retention > 200 years · Available for the following temperature ranges: - Commercial: 0°C to +70°C - Industrial: -40°C to +85°C
PACKAGE TYPES
PDIP
A PP V A2 1 A7 A6 A5 A4 A3 A2 A1 O0 O0 O1 V2
SS
·1 3 2 4 5 6 7 8 9 1 10 11 12 13 4
28 2 27 26 25 24 23 22 21 10 19 18 17 16 5
A VCC A14 A13 A8 A9 O11 AE C10 OE O7 O6 O5 O4 3
27LV256
3 4
2
1
32
31
A6 A5 A4 A3 A2 A1 N0 OC 0
3
0
A7 V12 NPP VU Acc A14 13
6 5 7 8 9 1 10 11 12 3 14 15 16 17 18 29 0 29 28 27 26 25 24 23 22 1
PLCC
A8 A9 N11 OC AE C10 OE O7 6
SOIC
VPP AA2 1 A7 A6 A5 A4 A3 A2 A1 O0 O0 O1 V2
SS
O1 V2 NS S OU O3 O4 5
2 1 3 4 5 6 7 8 9 1 10 11 12 13 4
27LV256
28 27 26 25 24 23 22 21 10 19 18 17 16 5
DESCRIPTION
The Microchip Technology Inc. 27LV256 is a low voltage (3.0 volt) CMOS EPROM designed for battery powered applications. The device is organized as a 32K x 8 (32K-Byte) non-volatile memory product. The 27LV256 consumes only 8 mA maximum of active current during a 3.0 volt read operation therefore improving battery performance. This device is designed for very low voltage applications where conventional 5.0 volt only EPROMS can not be used. Accessing individual bytes from an address transition or from power-up (chip enable pin going low) is accomplished in less than 200 ns at 3.0V. This device allows systems designers the ability to use low voltage non-volatile memory with today's' low voltage microprocessors and peripherals in battery powered applications. A complete family of packages is offered to provide the most flexibility in applications. For surface mount applications, PLCC, VSOP or SOIC packaging is available. Tape and reel packaging is also available for PLCC or SOIC packages.
V ACC A14 A13 A8 A9 O11 AE C10 OE O7 O6 O5 O4 3
A
27LV256
VSOP
AE O A1 1 A9 8 A13 V14
CC
VPP AA2 1 7 A6 5 A4 3
22 23 4 25 26 27 8 2 1 3 4 5 7 6
21 10 9 18 7 16 5 14 13 2 11 9 0 8
C10 E O7 6 A O5 O4 3 VSS O2 O1 0 A0 1 A2
27LV256
© 1996 Microchip Technology Inc.
DS11020F-page 1
This document was created with FrameMaker 4 0 4
27LV256
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name A0-A14 CE OE VPP O0 - O7 VCC VSS NC NU
PIN FUNCTION TABLE
Function Address Inputs Chip Enable Output Enable Programming Voltage Data Output +5V or +3V Power Supply Ground No Connection; No Internal Connection Not Used; No External Connection Is Allowed
VCC and input voltages w.r.t. VSS ........ -0.6V to +7.25V VPP voltage w.r.t. VSS during programming ........ -0.6V to +14V Voltage on A9 w.r.t. VSS .... -0.6V to +13.5V Output voltage w.r.t. VSS ...... -0.6V to VCC +1.0V Storage temperature .. -65°C to +150°C Ambient temp. with power applied ..... -65°C to +125°C
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
READ OPERATION DC CHARACTERISTICS
VCC = +5V ±10% or 3.0V where indicated Commercial: Tamb = 0°C to +70°C Industrial: Tamb = -40°C to +85°C
Parameter Input Voltages Input Leakage Output Voltages Output Leakage Input Capacitance Output Capacitance Power Supply Current, Active
Part* all all all all all all C I
Status Logic "1" Logic "0" Logic "1" Logic "0" -- -- -- TTL input TTL input
Symbol VIH VIL ILI VOH VOL ILO CIN COUT ICC1 ICC2
Min. 2.0 -0.5 -10 2.4
Max. VCC+1 0.8 10 0.45
Units V V µA V V µA pF pF mA mA mA mA
Conditions
VIN = 0 to VCC IOH = -400 µA IOL = 2.1 mA VOUT = 0V to VCC VIN = 0V; Tamb = 25°C; f = 1 MHz VOUT = 0V; Tamb = 25°C; f = 1 MHz VCC = 5.5V; VPP = VCC f = 1 MHz; OE = CE = VIL; IOUT = 0 mA; VIL = -0.1 to 0.8V; VIH = 2.0 to VCC; Note 1
-10 -- -- -- --
10 6 12 20 @ 5.0V 8 @ 3.0V 25 @ 5.0V 10 @ 3.0V
Power Supply Current, Standby
C I all
TTL input TTL input CMOS input
ICC(S)
--
1 @ 3.0V 2 @ 3.0V 100 @ 3.0V
mA mA µA
CE=VCC ± 0.2V
* Parts: C=Commercial Temperature Range I =Industrial Temperature Ranges
Note 1: Typical active current increases .75 mA per MHz up to operating frequency for all temperature ranges.
DS11020F-page 2
© 1996 Microchip Technology Inc.
27LV256
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature: 27HC256-20 Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to O/P High Impedance Output Hold from Address CE or OE, whichever goes first Sym Min tACC tCE tOE tOFF tOH -- -- -- 0 0 Max 200 200 100 50 -- Min -- -- -- 0 0 Max 250 250 125 50 -- Min -- -- -- 0 0 Max 300 300 125 50 -- ns ns ns ns ns CE = OE = VIL OE = VIL CE = VIL VIH = 2.4V and VIL = 0.45V; VOH = 2.0V VOL = 0.8V 1 TTL Load + 100 pF 10 ns Commercial: Tamb = 0°C to +70°C Industrial: Tamb = -40°C to +85°C 27HC256-30 Units Conditions
27HC256-25
FIGURE 1-1:
VIH Address VIL VIH CE VIL
READ WAVEFORMS
Address valid
t CE(2)
VIH OE VIL VOH VOL t ACC t OE(2) High Z t OFF(1,3) t OH Valid Output High Z
Outputs O0 - O7
Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested.
© 1996 Microchip Technology Inc.
DS11020F-page 3
27LV256
TABLE 1-4: PROGRAMMING DC CHARACTERISTICS
Ambient Temperature: Tamb = 25°C ± 5°C VCC = 6.5V ± 0.25V, VPP = 13.0V ± 0.25V Parameter Input Voltages Input Leakage Output Voltages VCC Current, program & verify VPP Current, program A9 Product Identification Status Logic"1" Logic"0" -- Logic"1" Logic"0" -- -- -- Symbol VIH VIL ILI VOH VOL ICC2 IPP2 VH Min 2.0 -0.1 -10 2.4 0.45 -- -- 11.5 20 25 12.5 Max. VCC+1 0.8 10 Units V V µA V V mA mA V VIN = 0V to VCC IOH = -400 µA IOL = 2.1 mA Note 1 Note 1 Conditions
Note 1: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
TABLE 1-5:
PROGRAMMING AC CHARACTERISTICS
AC Testing Waveform: VIH=2.4V and VIL=0.45V; VOH=2.0V; VOL=0.8V Output Load: 1 TLL Load + 100pF Ambient Temperature: Tamb=25°C±5°C VCC= 6.5V ± 0.25V, VPP =13.0V ± 0.25V Symbol tAS tDS tDH tAH tDF tVCS tPW tCES tOES tVPS tOE Min. 2 2 2 0 0 2 95 2 2 2 -- Max. -- -- -- -- 130 -- 105 -- -- -- 100 Units µs µs µs µs ns µs µs µs µs µs ns 100 µs typical Remarks
for Program, Program Verify and Program Inhibit Modes
Parameter Address Set-Up Time Data Set-Up Time Data Hold Time Address Hold Time Float Delay (2) VCC Set-Up Time Program Pulse Width (1) CE Set-Up Time OE Set-Up Time VPP Set-Up Time Data Valid from OE
Note 1: For express algorithm, initial programming width tolerance is 100 µs ±5%. 2: This parameter is only sampled and not 100% tested. Output float is defined as the point where data is no longer driven (see timing diagram).
DS11020F-page 4
© 1996 Microchip Technology Inc.
27LV256
FIGURE 1-2: PROGRAMMING WAVEFORMS
Program VIH Address VIL t AS VIH Data VIL t DS 13.0V(2) VPP 5.0V 6.5V(2) VCC 5.0V VIH CE VIL VIH OE VIL Notes: t PW t OPW t OES t OE (1) t VCS t VPS Data Stable t DH High Z Data Out Valid t DF (1) t AH Address Stable Verify
(1) t DF and tOE are characteristics of the device but must be accommodated by the programmer (2) VCC = 6.5V ±0.25V, V PP = VH = 13.0V ±0.25V for express algorithm
TABLE 1-6:
MODES
CE VIL VIL VIH VIH VIH VIL VIL OE VIL VIH VIL VIH X VIH VIL VPP VCC VH VH VH VCC VCC VCC A9 X X X X X X VH O0 - O7 DOUT DIN DOUT High Z High Z High Z Identity Code
Operation Mode Read Program Program Verify Program Inhibit Standby Output Disable Identity
X = Don't Care
1.2
Read Mode
(See Timing Diagrams and AC Characteristics) Read Mode is accessed when: a) b) the CE pin is low to power up (enable) the chip the OE pin is low to gate the data to the output pins
For Read operations, if the addresses are stable, the address access time (tACC) is equal to the delay from CE to output (tCE). Data is transferred to the output after a delay from the falling edge of OE (tOE).
© 1996 Microchip Technology Inc.
DS11020F-page 5
Others parts begin by 27
27-1 27-2 27-3 27-4 27-5 27-6
|
|
|
