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Part: 28C64AFT15I/P
Category:
Memory
-> ROM
-> EEPROM
-> Parallel
Description: Note:this Product Has Become 'Obsolete' And is no Longer Offered as a Viable Device For Design
Company: Microchip Technology, Inc.
Datasheet: Download 28C64AFT15I/P datasheet File size : 99 kB
Request For quote: Find where to buy 28C64AFT15I/P
Datasheet text preview:
28C64A
64K (8K x 8) CMOS EEPROM
FEATURES
· Fast Read Access Time--150 ns · CMOS Technology for Low Power Dissipation - 30 mA Active - 100 µA Standby · Fast Byte Write Time--200 µs or 1 ms · Data Retention >200 years · High Endurance - Minimum 100,000 Erase/Write Cycles · Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches · Data Polling · Ready/Busy · Chip Clear Operation · Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit · Electronic Signature for Device Identification · 5-Volt-Only Operation · Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin PLCC Package - 28-pin SOIC Package · Available for Extended Temperature Ranges: - Commercial: 0°C to +70°C - Industrial: -40°C to +85°C
PACKAGE TYPES
RDY/BSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
·1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vcc WE NC A8 A6 A9 A5 A11 A4 A3 OE A10 A2 A1 CE A0 I/O7 NC I/O6 I/O0 I/O5 I/O4 I/O3
2 RDY/BSY 1 NU
4 A7 3 A12
32 Vcc 31 WE 18 19
30 NC 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6 20
5 6
14
15
16
· Pin 1 indicator on PLCC on top of package
BLOCK DIAGRAM
I/O0 I/O7
VSS VCC CE
OE WE
Rdy/ Busy
Data Protection Circuitry Chip Enable/ Output Enable Control Logic
Auto Erase/Write Timing
Data Poll
Program Voltage Generation
A0
L a t c h e s
A12
Y Decoder
X Decoder
DESCRIPTION
The Microchip Technology Inc. 28C64A is a CMOS 64K nonvolatile electrically Erasable PROM. The 28C64A is accessed like a static RAM for the read or write cycles without the need of external components. During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wiredor systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications.
© 1998 Microchip Technology Inc.
I/O1 I/O2 Vss NU I/O3 I/O4 I/O5
Input/Output Buffers
Y Gating
16K bit Cell Matrix
DS11109J-page 1
17
DIP/SOIC
P LC C
7 8 9 10 11 12 13
28C64A
1.0
1.1
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS*
TABLE 1-1:
Name A0 - A12 CE OE WE I/O0 - I/O7 RDY/Busy VCC VSS NC NU
PIN FUNCTION TABLE
Function Address Inputs Chip Enable Output Enable W r ite Enable Data Inputs/Outputs Ready/Busy +5V Power Supply Ground No Connect No Inter nal Connection ; Not Used No Exter nal Connection is ; All owed
VCC and input voltagesw.r.t. V SS ....... -0.6V to + 6.25V Voltage on OE w.r.t. VSS ............ 0.6V to +13.5V ..Voltage on A9w.r.t. V SS .... 0.6V to +13.5V Output Voltage w.r.t. VSS........ 0.6V to V CC+0.6V .Storage temperatur .. 65°C to +125°C e Ambient temp. with power applied........ -50°C to +95°C
*Notice: Stresses abve those listed unde "Maxi mum Ratings" o r may cause pemanent damage to the evice. This is a stress r d rating only and functional ope ation of the device at those or a y r n other conditions ab ve those indicated in the ope tion listings of o ra this specification is not implied Exposure to maxi um r ating con. m ditions for extended pe iods may affect device reliabilit y. r
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTIC
VCC = +5V ±10% Commercial (C): Tamb = 0°C to +70°C Indust r ial (I): Tamb = -40°C to +85°C
Parameter Input Voltages Input Leakage Input Capacitance Output Voltages Output Leakage Output Capacitance Power Supply Current, Acti ve Power Supply Current, Standby
Status Logic `1' Logic `0' -- -- Logic `1' Logic `0' -- -- TTL input
Symbol VIH VIL I LI C IN VOH VOL I LO C OUT ICC
Min 2.0 -0.1 -10 -- 2.4
Max Vcc+1 0.8 10 10
Units V V µA pF V V µA pF mA mA mA µA
Conditions
VIN = -0.1V to Vcc +1 V IN = 0V; Tamb = 25°C; f = 1 MHz (Note 2) IOH = -400 µA IOL = 2.1 mA VOUT = -0.1V to Vcc +0.1V V IN = 0V; Tamb = 25°C; f = 1 MHz (Note 2) f = 5 MHz (Note 1) VCC = 5.5V CE = V IH (0°C to +70°C) CE = V IH (-40°C to +85°C) CE = V CC-0.3 to Vcc +1 OE = WE = Vcc All other inputs equal V CC or VSS
0.45 -10 -- -- -- 10 12 30 2 3 100
TTL input ICC(S)TTL TTL input ICC(S)TTL CMOS input ICC(S)CMOS
Note 1: AC power supply current above 5MHz: 2mA/MHz. 2: Not 100% tested.
DS11109J-page 2
© 1998 Microchip Technology Inc.
28C64A
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature:
28C64A-15
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C
28C64A-20 28C64A-25
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE High to Output Float Output Hold from Address, CE or OE, whichever occurs first. Endurance
Symbol Min tACC tCE tOE tOFF tOH -- -- -- -- 0 0 1M Max 150 150 70 50 -- -- Min -- -- -- 0 0 1M Max 200 200 80 55 -- -- Min -- -- -- 0 0 1M Max 250 250 100 70 -- --
Units ns ns ns ns ns
Conditions OE = CE = VIL OE = VIL CE = VIL (Note 1) (Note 1)
cycles 25°C, Vcc = 5.0V, Block Mode (Note 2)
Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
VIH Address VIL VIH CE VIL
READ WAVEFORMS
Address Valid
t CE(2)
VIH OE VIL VOH Data VOL t ACC VIH WE VIL Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested t OE(2) High Z t OFF(1,3) t OH Valid Output High Z
© 1998 Microchip Technology Inc.
DS11109J-page 3
28C64A
TABLE 1-4: BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise/Fall Times: Ambient Temperature: Parameter Address Set-Up Time Address Hold Time Data Set-Up Time Data Hold Time Write Pulse Width Write Pulse High Time OE Hold Time OE Set-Up Time Data Valid Time Time to Device Busy Write Cycle Time (28C64A) Write Cycle Time (28C64AF) Symbol tAS tAH tDS tDH tWPL tWPH tOEH tOES tDV tDB tWC tWC Min 10 50 50 10 100 50 10 10 -- 2 -- -- VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Max -- -- -- -- -- -- -- -- 1000 50 1 200 Units ns ns ns ns ns ns ns ns ns ns ms µs 0.5 ms typical 100 µs typical Note 2 Note 1 Remarks
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the positive edge WE, whichever occurs first. 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2:
PROGRAMMING WAVEFORMS
VIH Address VIL VIH CE, WE VIL t DV Data In VIH VIL t OES VIH OE VIL t OEH VOH Rdy/Busy VOL t WC t DB Busy Ready t DS t AS t AH t WPL t DH
DS11109J-page 4
© 1998 Microchip Technology Inc.
28C64A
FIGURE 1-3:
VIH
Address VIL Address Valid t ACC t CE t WPH
DATA POLLING WAVEFORMS
Last Written Address Valid
VIH
CE VIL
VIH
WE VIL
t WPL t OE
VIH
OE VIL
t DV VIH
Data VIL Data In Valid t WC I/O7 Out True Data Out
FIGURE 1-4:
VIH CE VIL VH OE VIH VIH WE VIL
CHIP CLEAR WAVEFORMS
tS
tW
tH
tW = 10ms tS = tH = 1µs VH = 12.0V ±0.5V
TABLE 1-5:
Mode Chip Clear Extra Row Read Extra Row Write Note:
SUPPLEMENTARY CONTROL
CE VIL VIL * OE VIH VIL VIH WE VIL VIH * A9 X A9 = VH A9 = VH VCC VCC VCC VCC Data Out Data In I/OI
VH = 12.0V±0.5V.
*Pulsed per programming waveforms.
© 1998 Microchip Technology Inc.
DS11109J-page 5
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