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Part: 93C86-SN
Category:
Memory
-> ROM
-> EEPROM
Description: 8k/16k 5.0v Microwire Serial EePROM
Company: Microchip Technology, Inc.
Datasheet: Download 93C86-SN datasheet File size : 147 kB
Request For quote: Find where to buy 93C86-SN
Datasheet text preview:
93C76/86
8K/16K 5.0V Microwire® Serial EEPROM
FEATURES
· Single 5.0V supply · Low power CMOS technology - 1 mA active current typical · ORG pin selectable memory configuration 1024 x 8- or 512 x 16-bit organization (93C76) 2048 x 8- or 1024 x 16-bit organization (93C86) · Self-timed ERASE and WRITE cycles (including auto-erase) · Automatic ERAL before WRAL · Power on/off data protection circuitry · Industry standard 3-wire serial I/O · Device status signal during ERASE/WRITE cycles · Sequential READ function · 10,000,000 ERASE/WRITE cycles guaranteed · Data retention > 200 years · 8-pin PDIP/SOIC package · Temperature ranges supported - Commercial (C): 0°C to +70°C - Industrial -40°C to +85°C - Automotive (E) -40°C to +125°C
PACKAGE TYPES
DIP Package
CS CLK DI DO
1 2 3 4
8 7 6 5
VCC PE ORG VSS
93C76/86
SOIC Package 1 2 3 4 8 7 6 5
CS CLK DI DO
VCC PE ORG VSS
93C76/86
BLOCK DIAGRAM
VCC VSS
DESCRIPTION
The Microchip Technology Inc. 93C76/86 are 8K and 16K low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 bits depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low power non-volatile memory applications. These devices also have a Program Enable (PE) pin to allow the user to write protect the entire contents of the memory array. The 93C76/86 is available in standard 8-pin DIP and 8pin surface mount SOIC packages.
DI
Memor y Array
Address Decoder
Address Counter
Data Register
Output Buffer
DO
PE CS
Mode Decode Logic
CLK
Clock Generator
Microwire is a registered trademark of National Semiconductor Incorporated.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21132C-page 1
93C76/86
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
1.2
AC Test Conditions
AC Waveform: VLO = 2.0V VHI = Vcc - 0.2V VHI = 4.0V for (Note 1) (Note 2)
VCC ..7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to Vcc +1.0V Storage temperature .... -65°C to +150°C Ambient temp. with power applied........ -65°C to +125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins......4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability
Timing Measurement Reference Level Input Output Note 1: For VCC 4.0V 2: For VCC > 4.0V 0.5 VCC 0.5 VCC
TABLE 1-1:
Name CS CLK DI DO VSS ORG PE VCC
PIN FUNCTION TABLE
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Memor y Configuration Program Enable Power Supply
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted: VCC = +4.5V to +5.5V Commercial (C): Tamb = 0°C to -40°C Industrial (I): Tamb = -40°C to +85°C Automotive (E): Tamb = -40°C to +125°C Parameter High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Symbol VIH1 VIL1 VOL1 VOL2 VOH1 VOH2 ILI ILO CINT Min. 2.0 -0.3 -- -- 2.4 VCC-0.2 -10 -10 -- Max. VCC +1 0.8 0.4 0.2 -- -- 10 10 7 Units V V V V V V µA µA pF Conditions -- -- IOL = 2.1 mA; VCC = 4.5V IOL =100 µA; VCC = 4.5V IOH = -400 µA; VCC = 4.5V IOH = -100 µA; VCC = 4.5V. VIN = 0.1V to VCC VOUT = 0.1V to VCC (Note Note:) Tamb = +25°C, FCLK = 1 MHz FCLK = 2 MHz; VCC = 5.5V FCLK = 2 MHz; VCC = 5.5V CLK = CS = 0V; VCC = 5.5V
ICC write -- 3 mA ICC read -- 1.5 mA Standby current ICCS -- 100 µA Note: This parameter is periodically sampled and not 100% tested.
DS21132C-page 2
Preliminary
© 1996 Microchip Technology Inc.
93C76/86
TABLE 1-3: AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted: VCC = +4.5V to +5.5V Commercial (C): Tamb = 0°C to -40°C Industrial (I): Tamb = -40°C to +85°C Automotive (E): Tamb = -40°C to +125°C Parameter Clock frequency Clock high time Clock low time Chip select setup time Chip select hold time Chip select low time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time Program cycle time Symbol FCLK TCKH TCKL TCSS TCSH TCSL TDIS TDIH TPD TCZ TSV TWC TEC TWL -- Min. -- 300 200 50 0 250 100 100 -- -- -- -- -- -- 10M Max. 2 -- -- -- -- -- -- -- 400 100 500 10 15 30 -- Units MHz ns ns ns ns ns ns ns ns ns ns ms ms ms cycles Conditions Vcc 4.5V
Relative to CLK Relative to CLK Relative to CLK Relative to CLK CL = 100 pF (Note 1) CL = 100 pF ERASE/WRITE mode (Note 2) ERAL mode WRAL mode 25°C, VCC = 5.0V, Block Mode (Note 3)
Endurance
Note 1: This parameter is periodically sampled and not 100% tested. 2: Typical program cycle is 4 ms per word. 3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
TABLE 1-4:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93C76: ORG=1 (X16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address X A8 A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXXXX X A8 A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXXX X A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXXX 00XXXXXXXX Data In -- -- -- -- D15 - D0 D15 - D0 -- Data Out D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 29 13 13 13 29 29 13
TABLE 1-5:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93C76: ORG=0 (X8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXXXXX X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXXXX X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXXXX 00XXXXXXXXX Data In -- -- -- -- D7 - D0 D7 - D0 -- Data Out D7 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 22 14 14 14 22 22 14
© 1996 Microchip Technology Inc.
Preliminary
DS21132C-page 3
93C76/86
TABLE 1-6:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93C86: ORG=1 (X16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 X X X X X XXX A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 X X X X X XXX A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXXX 00XXXXXXXX Data In -- -- -- -- D15 - D0 D15 - D0 -- Data Out D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 29 13 13 13 29 29 13
TABLE 1-7:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93C86: ORG=0 (X8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXXXXX A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXXXX A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXXXX 00XXXXXXXXX Data In Data Out Req. CLK Cycles 22 14 14 14 22 22 14
-- D7 - D0 -- High-Z -- (RDY/BSY) -- (RDY/BSY) D7 - D0 (RDY/BSY) D7 - D0 (RDY/BSY) -- High-Z
DS21132C-page 4
Preliminary
© 1996 Microchip Technology Inc.
93C76/86
2.0 PRINCIPLES OF OPERATION
When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an Erase/Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high impedance state on the falling edge of the CS. low all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.
2.4
Data Protection
During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.
2.1
START Condition
The START bit is detected by the device if CS and DI are both HIGH with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is HIGH, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction are clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the READ operation, if A0 is a logic HIGH level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin.
2.3
Erase/Write Enable and Disable (EWEN, EWDS)
The 93C76/86 powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all Erase/Write functions and should fol-
© 1996 Microchip Technology Inc.
Preliminary
DS21132C-page 5
Others parts begin by 93
93-1 93-2
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