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Part: 93C86C
Category:
Memory
-> ROM
-> EEPROM
-> Serial
Description: Note:this Product is Not Recommended For Designs Please Consider Using:<br>product 93C86CThe 93C86 is a 4K-bit Low-voltage Serial Electrically Erasable Prom Memory With an Org Pin Selectable Memory Configuration of 2048 X 8-bits or 1024 X 16-bits
Company: Microchip Technology, Inc.
Datasheet: Download 93C86C datasheet File size : 147 kB
Request For quote: Find where to buy 93C86C
Datasheet text preview:
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
16K Microwire® Compatible Serial EEPROM
Device Selection Table
Part Number
93AA86A 93AA86B 93LC86A 93LC86B 93C86A 93C86B 93AA86C 93LC86C 93C86C
VCC Range
1.8-5.5 1.8-5-5 2.5-5.5 2.5-5.5 4.5-5.5 4.5-5.5 1.8-5.5 2.5-5.5 4. 5 - 5 . 5
ORG Pin
No No No No No No Yes Yes Yes
Word Size
8- b i t 16-bit 8- b i t 16-bit 8- b i t 16-bit 8 or 16-bit 8 or 16-bit 8 or 16-bit
Temp Ranges
I I I, E I, E I, E I, E I I, E I, E
Pa c k a g e s
OT OT OT OT OT OT P, SN, ST, MS P, SN, ST, MS P, SN, ST, MS
Features
· · · · · · · · · · · · · · Low-power CMOS technology ORG pin to select word size for `86C' version 2048 x 8-bit organization `A' devices (no ORG) 1024 x 16-bit organization `B' devices (no ORG) Program Enable pin to write-protect the entire array Self-timed ERASE/WRITE cycles (including auto-erase) Automatic ERAL before WRAL Power on/off data protection circuitry Industry standard 3-wire serial I/O Device STATUS signal (READY/BUSY) Sequential READ function 1,000,000 E/W cycles Data retention > 200 years Temperature ranges supported: - Industrial (I) - Automotive (E) -40°C to +85°C -40°C to +125°C
Description
The Microchip Technology Inc. 93XX86A/B/C devices are 16K bit low-voltage serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as the 93XX86C are dependent upon external logic levels driving the ORG pin to set word size. For dedicated 8-bit communication, the 93XX86A devices are available, while the 93XX86B devices provide dedicated 16-bit communication. A Program Enable (PE) pin allows the user to write-protect the entire memory array. Advanced CMOS technology makes these devices ideal for low-power, nonvolatile memory applications. The entire 93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, 6-lead SOT-23, and 8-lead TSSOP. Pb-free (Pure Matte Sn) finish is also available.
Package Types (not to scale)
PDIP/SOIC
(P, SN)
CS CLK 1 2 3 4 8 7 6 5 VCC PE ORG VSS
SOT-23
(OT)
DO VSS DI 1 2 3 6 5 4 VCC CS CLK
Pin Function Table
Name
CS CLK DI DO V SS PE ORG VCC
Function
Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Program Enable Memory Configuration Power Supply
DI DO
TSSOP/MSOP
(ST, MS)
CS CLK DI DO 1 2 3 4 8 7 6 5 VCC PE ORG VSS
Microwire is a registered trademark of National Semiconductor.
2003 Microchip Technology Inc.
DS21797B-page 1
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings ()
VCC ........... 7.0V All inputs and outputs w.r.t. VSS ......... -0.6V to VCC +1.0V Storage temperature ............. -65°C to +150°C Ambient temperature with power applied ...... -40°C to +125°C ESD protection on all pins ............ 4 kV
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
All parameters apply over the specified ranges unless otherwise noted. Param. Symbol No. D1 D2 D3 D4 D5 D6 D7 D8 D9 VIH1 VIH2 VIL1 VIL2 Vol1 Vol2 VOH1 VOH2 ILI ILO CIN, COUT Parameter High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/ outputs) VCC = range by device (see Table on Page 1) Industrial (I): TAMB = -40°C to +85°C Automotive (E): TAMB = -40°C to +125°C Min 2 .0 0.7 VCC -0.3 -0.3 -- -- 2 .4 VCC - 0.2 -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- 500 -- -- 100 -- -- M ax VCC +1 VCC +1 0.8 0.2 VCC 0.4 0.2 -- -- ±10 ±10 7 3 -- 1 500 -- 1 5 Units V V V V V V V V µA µA pF mA µA mA µA µA µA µA Conditions VCC 2.7V VCC < 2.7V VCC 2.7V VCC < 2.7V IOL = 2.1 mA, VCC = 4.5V IOL = 100 µA, VCC = 2.5V IOH = -400 µA, VCC = 4.5V IOH = -100 µA, VCC = 2.5V VIN = VSS to VCC VOUT = VSS to VCC VIN/VOUT = 0V (Note 1) TAMB = 25°C, FCLK = 1 MHz FCLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 2.5V FCLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 3.0V FCLK = 2 MHz, VCC = 2.5V I Temp E Temp CLK = Cs = 0V ORG = DI = VSS or VCC (Note 2) (Note 3) (Note 1)
ICC write Write current ICC read Read current
D10
ICCS
Standby current
D11
VPOR
VCC voltage detect 93AA86A/B/C, 93LC86A/B/C 93C86A/B/C
-- --
1.5V 3.8V
-- --
V V
Note 1: 2: 3:
This parameter is periodically sampled and not 100% tested. ORG pin not available on `A' or `B' versions. READY/BUSY status must be cleared from DO, see Section 3.4 "Data Out (DO)".
DS21797B-page 2
2003 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
AC CHARACTERISTICS
All parameters apply over the specified ranges unless otherwise noted. Param. Symbol No. A1 FCLK Parameter Clock frequency VCC = range by device (see Table on Page 1) Industrial (I): TAMB = -40°C to +85°C Automotive (E): TAMB = -40°C to +125°C Min -- Max 3 2 1 -- Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms Conditions 4.5V VCC < 5.5V 2.5V VCC < 4.5V 1.8V VCC < 2.5V 4.5V VCC < 5.5V 2.5V VCC < 4.5V 1.8V VCC < 2.5V 4.5V VCC < 5.5V 2.5V VCC < 4.5V 1.8V VCC < 2.5V 4.5V VCC < 5.5V 2.5V VCC < 4.5V 1.8V VCC < 2.5V 1.8V VCC < 5.5V 1.8V VCC < 5.5V 4.5V VCC < 5.5V 2.5V VCC < 4.5V 1.8V VCC < 2.5V 4.5V VCC < 5.5V 2.5V VCC < 4.5V 1.8V VCC < 2.5V 4.5V VCC < 5.5V, CL = 100 pF 2.5V VCC < 4.5V, CL = 100 pF 1.8V VCC < 2.5V, CL = 100 pF 4.5V VCC < 5.5V, (Note 1) 1.8V VCC < 4.5V, (Note 1) 4.5V VCC < 5.5V, CL = 100 pF 2.5V VCC < 4.5V, CL = 100 pF 1.8V VCC < 2.5V, CL = 100 pF ERASE/WRITE mode (AA and LC versions) ERASE/WRITE mode (93C versions) ERAL mode, 4.5V VCC 5.5V WRAL mode, 4.5V VCC 5.5V
A2
TCKH
Clock high time
200 250 450 100 200 450 50 100 250 0 250 50 100 250 50 100 250 --
A3
TCKL
Clock low time
--
A4
TCSS
Chip select setup time
--
A5 A6 A7
TCSH TCSL TDIS
Chip select hold time Chip select low time Data input setup time
-- -- --
A8
TDIH
Data input hold time
--
A9
TPD
Data output delay time
100 250 400 100 200 200 300 500 6 2 6 15 --
A10 A11
TCZ TSV
Data output disable time Status valid time
-- --
A12 A13 A14 A15 A16 Note 1: 2:
TWC TWC TEC TWL --
Program cycle time
-- -- -- --
Endurance
1M
cycles 25°C, VCC = 5.0V, (Note 2)
This parameter is periodically sampled and not 100% tested. This application is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which may be obtained on www.microchip.com.
2003 Microchip Technology Inc.
DS21797B-page 3
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
FIGURE 1-1:
CS VIH VIL CLK VIH VIL TDIS VIH DI VIL DO (READ) VOH VOL TSV STATUS VALID TPD TPD TCZ TDIH TCSS TCKH TCKL TCSH
SYNCHRONOUS DATA TIMING
TCZ
DO VOH (PROGRAM) VOL Note: TSV is relative to CS.
TABLE 1-1: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX86B OR 93XX86C WITH ORG = 1)
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A 9 A 8 A7 A 6 A5 A 4 A3 A 2 A 1 A0 1 1 X X X X X X X X Data In -- -- -- -- Data Out D15 D0 HIGH-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) HIGH-Z Req. CLK Cycles 29 13 13 13 29 29 13
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 X X X X X X X X
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D0 0 0 1 0 X X X X X X X X X X X X X X X X D15 D0 --
TABLE 1-2: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX86A OR 93XX86C WITH ORG = 0)
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 X X X X X X X X X Data In -- -- -- -- Data Out D7 D0 HIGH-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) HIGH-Z Req. CLK Cycles 22 14 14 14 22 22 14
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 X X X X X X X X X
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D0 0 0 1 0 X X X X X X X X X X X X X X X X X X D7 D0 --
DS21797B-page 4
2003 Microchip Technology Inc.
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.0 FUNCTIONAL DESCRIPTION
2.2 Data In/Data Out (DI/DO)
When the ORG* pin is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/ BUSY status during a programming operation. The READY/BUSY status can be verified during an Erase/ Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. DO will enter the HIGH-Z state on the falling edge of CS. It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the read operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO.
2.3
Data Protection
2.1
START Condition
The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, or WRAL). As soon as CS is high, the device is no longer in Standby mode. An instruction following a START condition will only be executed if the required opcode, address and data bits for any particular instruction are clocked in.
All modes of operation are inhibited when VCC is below a typical voltage of 1.5V for `93AA' and `93LC' devices or 3.8V for `93C' devices. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. Note: For added protection, an EWDS command should be performed after every write operation.
After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before the initial ERASE or WRITE instruction can be executed.
Block Diagram
VCC VSS Address Decoder Address Counter Data Register DI ORG* CS PE CLK Clock Register Mode Decode Logic Output Buffer DO
Memory Array
*ORG and PE inputs are not available on A/B devices.
2003 Microchip Technology Inc.
DS21797B-page 5
Others parts begin by 93
93-1 93-2
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