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Part: 93LC46-SL
Category:
Memory
-> ROM
-> EEPROM
Description: 1k/2k/4k 2.0v Microwire Serial EePROM
Company: Microchip Technology, Inc.
Datasheet: Download 93LC46-SL datasheet File size : 140 kB
Request For quote: Find where to buy 93LC46-SL
Datasheet text preview:
M
FEATURES
93LC46/56/66
BLOCK DIAGRAM
VCC VSS
1K/2K/4K 2.0V Microwire® Serial EEPROM
· Single supply with programming operation down to 2.0V (Commercial only) · Low power CMOS technology - 1 mA active current typical - 5 µA standby current (typical) at 3.0V · ORG pin selectable memory configuration - 128 x 8 or 64 x 16-bit organization (93LC46) - 256 x 8 or 128 x 16-bit organization(93LC56) - 512 x 8 or 256 x 16-bit organization(93LC66) · Self-timed ERASE and WRITE cycles (including auto-erase) · Automatic ERAL before WRAL · Power on/off data protection circuitry · Industry standard 3-wire serial I/O · Device status signal during ERASE/WRITE cycles · Sequential READ function · 10,000,000 ERASE/WRITE cycles guaranteed on 93LC56 and 93LC66 · 1,000,000 E/W cycles guaranteed on 93LC46 · Data retention > 200 years · 8-pin PDIP/SOIC and 14-pin SOIC package (SOIC in JEDEC and EIAJ standards) · Temperature ranges supported - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C
MEMORY ARRAY
ADDRESS DECODER
ADDRESS COUNTER
DATA REGISTER DI MODE DECODE LOGIC
OUTPUT BUFFER
DO
CS
CLK
CLOCK GENERATOR
DESCRIPTION
The Microchip Technology Inc. 93LC46/56/66 are 1K, 2K, and 4K low-voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 bits, depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low-power, nonvolatile memory applications. The 93LC46/56/66 is available in standard 8-pin DIP and 8/ 14-pin surface mount SOIC packages. The 93LC46X/ 56X/66X are only offered in an "SN" package.
PACKAGE TYPES
SOIC
NC 1 2 14 13 NC Vcc NU NC ORG VSS NC
DIP
CS CLK DI DO 1 8 VCC NU ORG VSS 1
SOIC
8 VCC NU ORG VSS 1
SOIC
8 ORG VSS DO DI
CS CLK
93LC56 93LC66
3 4 5 6 7
12 11 10 9 8
CS CLK DI DO
NU VCC CS CLK
NC DI DO NC
93LC46 93LC56 93LC66
93LC46 93LC56 93LC66
93LC46X 93LC56X 93LC66X
2 3 4
7 6 5
2 3 4
7 6 5
2 3 4
7 6 5
© 1997 Microchip Technology Inc.
DS11168L-page 1
93LC46/56/66
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
PIN function Table
Name CS CLK DI DO VSS ORG NU NC VCC
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Memory Configuration Not Utilized No Connect Power Supply
Vcc .. 7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to Vcc +1.0V Storage temperature .... -65°C to +150°C Ambient temp. with power applied........ -65°C to +125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins......4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1
DC AND AC ELECTRICAL CHARACTERISTICS
Commercial (C): Vcc = +2.0V to +6.0V (C): Tamb = 0°C to +70°C Industrial (I): Vcc = +2.5V to +6.0V (I): Tamb = -40°C to +85°C Symbol Min. Max. Units Conditions
Parameter
High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Clock frequency Clock high time Clock low time Chip select setup time Chip select hold time Chip select low time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time Program cycle time Endurance 93LC46 93LC56/66
Note 1: 2: 3: 4:
VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 VOH1 VOH2 ILI ILO CIN, COUT ICC read ICC write ICCS FCLK TCKH TCKL TCSS TCSH TCSL TDIS TDIH TPD TCZ TSV TWC TEC TWL -- --
2.0 0.7 Vcc -0.3 -0.3 -- -- 2.4 Vcc-0.2 -10 -10 -- -- -- -- -- 250 250 50 0 250 100 100 -- -- -- -- -- -- 1M 10M
Vcc +1 Vcc +1 0.8 0.2 Vcc 0.4 0.2 -- -- 10 10 7 1 500 3 100 30 2 1 -- -- -- -- -- -- -- 400 100 500 10 15 30 -- --
V V V V V V V V µA µA pF mA µA mA µA µA MHz MHz ns ns ns ns ns ns ns ns ns ns ms ms ms cycles
VCC 2.7V VCC < 2.7V VCC 2.7V VCC < 2.7V IOL = 2.1 mA; Vcc = 4.5V IOL =100 µA; Vcc = Vcc Min. IOH = -400 µA; Vcc = 4.5V IOH = -100 µA; Vcc = Vcc Min. VIN = 0.1V to Vcc VOUT = 0.1V to Vcc VIN/VOUT = 0 V (Notes 1 & 3) Tamb = +25°C, FCLK = 1 MHz FCLK = 2 MHz; Vcc = 6.0V FCLK = 1 MHz; Vcc = 3.0V FCLK = 2 MHz; Vcc = 6.0V (Note 3) CLK = CS = 0V; Vcc = 6.0V CLK = CS = 0V; Vcc = 3.0V Vcc 4.5V Vcc < 4.5V
Relative to CLK Relative to CLK Relative to CLK Relative to CLK CL = 100 pF CL = 100 pF (Note 3) CL = 100 pF ERASE/WRITE mode (Note 2) ERAL mode WRAL mode 25°C, Vcc = 5.0V, Block Mode (Note 4)
This parameter is tested at Tamb = 25°C and FCLK = 1 MHz. Typical program cycle time is 4 ms per word. This parameter is periodically sampled and not 100% tested. This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS11168L-page 2
© 1997 Microchip Technology Inc.
93LC46/56/66
2.0
2.1
PIN DESCRIPTION
Chip Select (CS)
2.3
Data In (DI)
Data In (DI) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.
A high level selects the device. A low level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a RESET status.
2.4
Data Out (DO)
Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held low or high during the entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, a pull-up resistor on DO is required to read the READY signal.
2.2
Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the communication between a master device and the 93LCXX. Opcodes, addresses, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing the opcode, address, and data. CLK is a "Don't Care" if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detecting a START condition, the specified number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcodes, addresses, and data bits before an instruction is executed (Table 2-1 to Table 2-6). CLK and DI then become don't care inputs waiting for a new START condition to be detected. Note: CS must go low between consecutive instructions.
2.5
Organization (ORG)
When ORG is tied to VSS, the (x8) memory organization is selected. When ORG is connected to Vcc or floated, the (x16) memory organization is selected. ORG can only be floated for clock speeds of 1 MHz or less for the (X16) memory organization. For clock speeds greater than 1 MHz, ORG must be tied to Vcc or VSS.
© 1997 Microchip Technology Inc.
DS11168L-page 3
93LC46/56/66
TABLE 2-1
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 11 00 00 00 10 01 00 Address A6 A5 A4 A3 A2 A1 A0 10XXXXX 00XXXXX 11XXXXX A6 A5 A4 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 01XXXXX Data In -- -- -- -- -- D7 - D0 D7 - D0 Data Out (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z D7 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 10 10 10 10 18 18 18
TABLE 2-2
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 11 00 00 00 10 01 00 Address A5 A4 A3 A2 A1 A0 10XXXX 00XXXX 11XXXX A5 A4 A3 A2 A1 A0 A5 A4 A3 A2 A1 A0 01XXXX Data In -- -- -- -- -- D15 - D0 D15 - D0 Data Out (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z D15 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 9 9 9 9 25 25 25
TABLE 2-3
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 11 00 00 00 10 01 00 Address X A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXX 00XXXXXXX 11XXXXXXX X A7 A6 A5 A4 A3 A2 A1 A0 X A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXX Data In -- -- -- -- -- D7 - D0 D7 - D0 Data Out (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z D7 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 12 12 12 12 20 20 20
TABLE 2-4
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 11 00 00 00 10 01 00 Address X A6 A5 A4 A3 A2 A1 A0 10XXXXXX 00XXXXXX 11XXXXXX X A6 A5 A4 A3 A2 A1 A0 X A6 A5 A4 A3 A2 A1 A0 01XXXXXX Data In -- -- -- -- -- D15 - D0 D15 - D0 Data Out (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z D15 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 11 11 11 11 27 27 27
TABLE 2-5
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 11 00 00 00 10 01 00 Address A8 A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXX 00XXXXXXX 11XXXXXXX A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXX Data In -- -- -- -- -- D7 - D0 D7 - D0 Data Out (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z D7 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 12 12 12 12 20 20 20
TABLE 2-6
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXX A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXX A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXX 00XXXXXX Data In -- -- -- -- D15 - D0 D15 - D0 -- Data Out D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 27 11 11 11 27 27 11
DS11168L-page 4
© 1997 Microchip Technology Inc.
93LC46/56/66
3.0 FUNCTIONAL DESCRIPTION
3.2 Data In (DI) and Data Out (DO)
When it is connected to ground, the (x8) organization is selected. When the ORG pin is connected to Vcc, the (x16) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state, except when reading data from the device or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS. It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the READ operation. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of Data Out, and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin.
3.3
Data Protection
3.1
START Condition
The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected.
During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 1.4V at nominal conditions. The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enable (EWEN) commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.
FIGURE 3-1:
CS
SYNCHRONOUS DATA TIMING
V IH V IL V IH TCSS TCKH TCKL TCSH
CLK V IL TDIS V IH DI V IL TPD DO (READ) V OH V OL TSV STATUS VALID TCZ TPD TCZ TDIH
DO V OH (PROGRAM) V OL
© 1997 Microchip Technology Inc.
DS11168L-page 5
Others parts begin by 93
93-1 93-2
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