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Details, datasheet, quote on part number:93LC46A-ISM
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Datasheet text preview:
93LC46A/B
1K 2.5V Microwire® Serial EEPROM
FEATURES
· Single supply with operation down to 2.5V · Low power CMOS technology - 1 mA active current (typical) - 1 µA standby current (maximum) · 128 x 8 bit organization (93LC46A) · 64 x 16 bit organization (93LC46B) · Self-timed ERASE and WRITE cycles (including auto-erase) · Automatic ERAL before WRAL · Power on/off data protection circuitry · Industry standard 3-wire serial interface · Device status signal during ERASE/WRITE cycles · Sequential READ function · 1,000,000 E/W cycles guaranteed · Data retention > 200 years · 8-pin PDIP/SOIC and 8-pin TSSOP packages · Available for the following temperature ranges: - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C
BLOCK DIAGRAM
MEMORY ARRAY ADDRESS DECODER
ADDRESS COUNT ER DATA REGISTER DI MODE DECODE LOGIC CLOCK GENERATOR Vcc Vss OUTPUT BUFFER
DO
CS CLK
DESCRIPTION
The Microchip Technology Inc. 93LC46AX/BX are 1Kbit, low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC46A) or x16 bits (93LC46B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC46AX/BX is available in standard 8-pin DIP, 8-pin surface mount SOIC, and TSSOP packages. The 93LC46AX/BX are offered only in a 150-mil SOIC package.
PACKAGE TYPE
DI P CS CLK DI DO 1 8 Vcc CS 7 6 5 NC CL K NC Vss DO DI SOIC SOIC CS CLK DI DO 1 2 3 4 TSSOP
93LC46A/B
1
8
VCC NC NC Vss
NC Vcc CS CLK
1 2 3 4
8 7 6 5
NC Vss DO DI
2 3 4
2 3 4
7 6 5
8 7 6 5
V cc NC NC V ss
93LC46AX/BX
Microwire is a registered trademark of National Semiconductor Incorporated.
2000 Microchip Technology Inc.
93LC46A/B
93LC46A/B
DS 21173E - page 1
93LC46A/B
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1
Name CS CLK DI DO VSS NC VCC
PIN FUNCTION TABLE
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground No Connect Power Supply
Vcc .. 7.0V All inputs and outputs w.r.t. Vss ...... -0.6V to Vcc +1.0V Storage temperature .... -65°C to +150°C Ambient temp. with power applied ....... -65°C to +125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins......4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2
DC AND AC ELECTRICAL CHARACTERISTICS
Commercial (C): Industrial (I): Symbol VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 VOH1 VOH2 ILI ILO CIN, COUT ICC write VCC = +2.5V to +6.0V VCC = +2.5V to +6.0V Min. 2.0 0.7 VCC -0.3 -0.3 -- -- 2.4 VCC-0.2 -10 -10 -- -- -- -- -- 250 250 50 0 250 100 100 -- -- -- -- -- -- 1M Max. Vcc +1 Vcc +1 0.8 0.2 Vcc 0.4 0.2 -- -- 10 10 7 1.5 1 500 1 2 1 -- -- -- -- -- -- -- 400 100 500 6 6 15 -- Tamb = 0°C to +70°C Tamb = -40°C to +85°C Units V V V V V V V V µA µA pF mA mA µA µA MHz MHz ns ns ns ns ns ns ns ns ns ns ms ms ms cycles Relative to CLK Relative to CLK CL = 100 pF CL = 100 pF (Note 2) CL = 100 pF ERASE/WRITE mode ERAL mode WRAL mode 25°C, VCC = 5.0V, Block Mode (Note 3) Relative to CLK Relative to CLK FCLK = 2 MHz; Vcc = 6.0V FCLK = 1 MHz; Vcc = 3.0V CS = Vss; DI = VSS VCC > 4.5V VCC 2.7V (Note 2) VCC < 2.7V IOL = 2.1 mA; Vcc = 4.5V IOL =100 µA; Vcc = Vcc Min. IOH = -400 µA; Vcc = 4.5V IOH = -100 µA; Vcc = Vcc Min. VIN = VSS to Vcc VOUT = VSS to Vcc VIN/VOUT = 0 V (Notes 1 & 2) Tamb = +25°C, FCLK = 1 MHz
All parameters apply over the specified operating ranges unless otherwise noted Parameter High level input voltage
Low level input voltage
Low level output voltage
High level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Clock frequency Clock high time Clock low time Chip select setup time Chip select hold time Chip select low time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time
ICC read ICCS FCLK TCKH TCKL TCSS TCSH TCSL TDIS TDIH T PD TCZ TSV TWC
Program cycle time
TEC TWL
Endurance
--
Note 1: This parameter is tested at Tamb = 25°C and Fclk = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. 3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on our website.
DS2117 3E-page 2
2000 Microchip Technology Inc.
93LC46A/B
2.0
2.1
PIN DESCRIPTION
Chip Select (CS)
CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection of a START condition the specified number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected.
A high level selects the device; a low level deselects the device and forces it into standby mode. However, a programming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a RESET status.
2.3
Data In (DI)
Data In (DI) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.
2.2
Serial Clock (CLK)
2.4
Data Out (DO)
The Serial Clock is used to synchronize the communication between a master device and the 93LC46AX/ BX. Opcodes, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a "Don't Care" if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition).
Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready.
TABLE 2-1
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION SET FOR 93LC46A
SB
1 1 1 1 1 1 1
Opcode
11 00 00 00 10 01 00 A6 1 0 1 A6 A6 0 A5 0 0 1 A5 A5 1
Address
A4 X X X A4 A4 X A3 X X X A3 A3 X A2 X X X A2 A2 X A1 X X X A1 A1 X A0 X X X A0 A0 X
Data In
-- -- -- -- -- D7 - D0 D7 - D0
Data Out
(RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z D7 - D0 (RDY/BSY) (RDY/BSY)
Req. CLK Cycles
10 10 10 10 18 18 18
TABLE 2-2
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION SET FOR 93LC46B
SB
1 1 1 1 1 1 1
Opcode
11 00 00 00 10 01 00 A5 1 0 1 A5 A5 0 A4 0 0 1 A4 A4 1
Address
A3 X X X A3 A3 X A2 X X X A2 A2 X A1 X X X A1 A1 X A0 X X X A0 A0 X
Data In
-- -- -- -- -- D15 - D0 D15 - D0
Data Out
(RDY/BSY) (RDY/BSY) H I G H -Z H I G H -Z D15 - D0 (RDY/BSY) (RDY/BSY)
Req. CLK Cycles
9 9 9 9 25 25 25
2000 Microchip Technology Inc.
DS 21173E - page 3
93LC46A/B
3.0 FUNCTIONAL DESCRIPTION
Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected.
3.2
Data In (DI) and Data Out (DO)
3.1
START Condition
The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in.
It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the READ operation. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin.
3.3
Data Protection
During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions. The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enable (EWDS) commands give additional protection against accidentally programming during normal operation.
FIGURE 3-1:
CS
SYNCHRONOUS DATA TIMING
VIH VIL VIH TCSS TCKH TCKL TCSH
CLK VIL TDIS VIH DI VIL TPD VOH DO (READ) VOL DO VOH (PROGRAM) VOL Note: AC Test Conditions: VIL = 0.4V, VIH = 2.4V TPD TCZ TDIH
TCZ TSV STATUS VALID
DS2117 3E-page 4
2000 Microchip Technology Inc.
93LC46A/B
3.4 ERASE 3.5 Erase All (ERAL)
The ERASE instruction forces all data bits of the specified address to the logical "1" state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been erased and the device is ready for another instruction. The Erase All (ERAL) instruction will erase the entire memory array to the logical "1" state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire ERAL cycle is complete.
FIGURE 3-2:
CS
ERASE TIMING
TCSL CHECK STATUS
CL K
DI
1
1
1
AN
AN-1
AN-2
···
A0 TSV TCZ READY HIGH-Z TWC
DO
HIGH-Z
BUSY
FIGURE 3-3:
CS
ERAL TIMING
TCSL CHECK STATUS
CL K
DI
1
0
0
1
0
X
···
X TSV TCZ READY HIGH-Z TEC
DO
HIGH-Z
BUSY
Guaranteed at Vcc = 4.5V to +6.0V.
2000 Microchip Technology Inc.
DS 21173E - page 5
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