|
Details, datasheet, quote on part number:MT8VDDT3264AG-40B__
| |
Datasheet text preview:
128MB, 256MB (x64), PC3200 184-PIN DDR SDRAM DIMM
DDR SDRAM DIMM
Features
· · · · · · · · · · · · 184-pin dual in-line memory module (DIMM) Fast data transfer rates: PC3200 CAS Latency 3 Utilizes 400 MT/s DDR SDRAM components 128MB (16 Meg x 64) and 256MB (32 Meg x 64) VDD= VDDQ= +2.6V VDDSPD = +2.3V to +3.6V 2.6V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/ received with data--i.e., source-synchronous data capture Differential clock inputs (CK and CK#) Four internal device banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6µs (128MB), 7.8125µs (256MB) maximum average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Programmable READ CAS latency Gold edge connectors
MT8VDDT1664A 128MB MT8VDDT3264A 256MB
For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds
Figure 1: 184-Pin DIMM (MO-206)
OPTIONS
MARKING
· Package 184-pin DIMM (Standard) 184-pin DIMM (Lead-free) · Memory Clock/Speed, CAS Latency 5ns (200 MHz), 400 MT/s, CL = 3
G Y - 40B
· · · · · · · · ·
Table 1:
Address Table
128MB 256MB 8K 8K (A0A12) 4 (BA0, BA1) 32 Meg x 8 1K (A0A9) 1 (S0#) 4K 4K (A0A11) 4 (BA0, BA1) 16 Meg x 8 1K (A0A9) 1 (S0#)
Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
Table 2:
Part Numbers and Timing Parameters
MODULE DENSITY 128MB 128MB 256MB 256MB CONFIGURATION 16 Meg x 64 16 Meg x 64 32 Meg x 64 32 Meg x 64 MODULE BANDWITH 3.2 GB/s 3.2 GB/s 3.2 GB/s 3.2 GB/s MEMORYCLOCK/ DATA RATE 5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s LATENCY (CL - tRCD - tRP) 3-3-3 3-3-3 3-3-3 3-3-3
PARTNUMBER MT8VDDT1664AG-40B__ MT8VDDT1664AY-40B__ MT8VDDT3264AG-40B__ MT8VDDT3264AY-40B__
NO TE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3264AG-40BA1
09005ae f80867a9 9 DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN
1
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB (x64), PC3200 184-PIN DDR SDRAM DIMM
Table 3: Pin Assignment (184-Pin DIMM Front)
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 DNU DNU VDD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DNU A0 DNU VSS DNU BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS CK2# CK2 VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
Table 4:
Pin Assignment (184-Pin DIMM Back)
162 DQ47 163 NC 164 VDDQ 165 DQ52 166 DQ53 167 NC 168 VDD 169 DQS15/DM6 170 DQ54 171 DQ55 172 VDD 173 NC 174 DQ60 175 DQ61 176 VSS 177 DQS16/DM7 178 DQ62 179 DQ63 180 VDDQ 181 SA0 182 SA1 183 SA2 184 VDDSPD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
NO TE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 93 VSS 116 VSS 139 VSS 94 DQ4 117 DQ21 140 DNU 95 DQ5 118 A11 141 A10 DNU 96 VDDQ 119 DQS11/DM2 142 97 DQS9/DM0 120 VDD 143 VDDQ 98 DQ6 121 DQ22 144 DNU 99 DQ7 122 A8 145 VSS 100 VSS 123 DQ23 146 DQ36 101 NC 124 VSS 147 DQ37 102 NC 125 A6 148 VDD 103 NC 126 DQ28 149 DQS13/DM4 104 VDDQ 127 DQ29 150 DQ38 105 DQ12 128 VDDQ 151 DQ39 106 DQ13 129 DQS12/DM3 152 VSS 107 DQS10/DM1 130 A3 153 DQ44 108 VDD 131 DQ30 154 RAS# 109 DQ14 132 VSS 155 DQ45 110 DQ15 133 DQ31 156 VDDQ 111 DNU 134 DNU 157 S0# 112 VDDQ 135 DNU 158 DNU 113 NC 136 VDDQ 159 DQS14/DM5 114 DQ20 137 CK0 160 VSS 115 NC/A12 138 CK0# 161 DQ46
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1# VSS DQ10 DQ11 CKE0 VDDQ DQ16
Pin 115 is "No Connect" for the 128MB module, or "A12" for the 256MB module.
Figure 2: 184-Pin DIMM Pin Locations
Front View
U10
U1
U2
U3
U4
U6
U7
U8
U9
PIN 1
PIN 52
PIN 53
PIN 92
Back View
No Components This Side of Module
PIN 184
PIN 145
PIN 144
PIN 93
Indicates a VDD or VDDQ pin
Indicates a VSS pin
09005ae f80867a9 9 DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc.
128MB, 256MB (x64), PC3200 184-PIN DDR SDRAM DIMM
Table 5: Pin Descriptions
SYMBOL VREF WE#, CAS#, RAS# CK0, CK0#, CK1, CK1#, CK2, CK2# TYPE Input Input Input DESCRIPTION SSTL_2 reference voltage. Command Inputs: WE#, RAS#, and CAS# (along with S#) define the command being entered. Clocks: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE activates (HIGH) and deactivates (LOW) internal clock signals, device input buffers, and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. Chip Select: S# enables (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Bank Addresses: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: Sampled during the ACTIVE command (rowaddress) and READ/WRITE command (column-address, with A10 defining auto precharge) to select one location out of the memory array in the respective device device bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one device bank (A10 LOW) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presencedetect portion of the module. Data I/Os: Check bits. ECC, one-bit error detection and correction. Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 2 for more information PIN NUMBERS 1 63, 65, 154 16, 17, 75, 76, 137, 138
21
CKE0
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48, 115 (256MB), 118, 122, 125, 130, 141
A0-A11 128MB A0-A12 256MB
Input
91 92 181, 182, 183
SDA SCL SA0-SA2
Input/ Output Input Input
5, 14, 25, 36, 56, 67, 78, 86, 97, 107, 119, 129, 149, 159, 169, 177
DQS0DQS7, DQS9DQS16
Input/ Output
09005ae f80867a9 9 DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc.
|
|
