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Part: MT9VDDT3272AY-40B__
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> 256 MB
Description: 184-Pin DDR Sdram Dimm, Unbuffered, Ecc, PC3200, (x72)
Company: Micron Semiconductor Products, Inc.
Datasheet: Download MT9VDDT3272AY-40B__ datasheet File size : 2802 kB
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Datasheet text preview:
128MB, 256MB (x72, ECC), PC3200 184-Pin DDR SDRAM DIMM
DDR SDRAM DIMM
Features
· JEDEC-standard 184-pin dual in-line memory module (DIMM) · Fast data transfer rate: PC3200 · CAS Latency 3 · Utilizes 400 MT/s DDR SDRAM components · ECC-optimized pinout 128MB (16 Meg x 72), 256MB (32 Meg x 72) · VDD= VDDQ= +2.6V · VDDSPD = +2.3V to +3.6V · +2.6V I/O (SSTL_2 compatible) · Commands entered on each positive CK edge · DQS edge-aligned with data for READs; centeraligned with data for WRITEs · Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle · Bidirectional data strobe (DQS) transmitted/ received with data--i.e., source-synchronous data capture · Differential clock inputs (CK and CK#) · Four internal device banks for concurrent operation · Programmable burst lengths: 2, 4, or 8 · Auto precharge option · Auto Refresh and Self Refresh Modes · 15.6µs (128MB), 7.8125µs (256MB) maximum average periodic refresh interval · Serial Presence-Detect (SPD) with EEPROM · Programmable READ CAS latency · Gold edge contacts
MT9VDDT1672A 128MB MT9VDDT3272A 256MB
For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds
Figure 1: 184-Pin DIMM (MO-206)
OPTIONS · Package 184-pin DIMM (Standard) 184-pin DIMM (Lead-free) · Frequency/CAS Latency 5ns, 400 MT/s (200 MHz), CL = 3
MARKING G Y - 4 0B
Table 1:
Address Table
128MB 256MB 8K 8K (A0A12) 4 (BA0, BA1) 32 Meg x 8 1K (A0A9) 1 (S0#)
4K Refresh Count 4K (A0A11) Row Addressing Device Bank Addressing 4 (BA0, BA1) 16 Meg x 8 Device Configuration 1K (A0A9) Column Addressing 1 (S0#) Module Rank Addressing
Table 2:
Part Numbers and Timing Parameters
MODULE DENSITY 128MB 128MB 256MB 256MB CONFIGURATION 16 Meg x 72 16 Meg x 72 32 Meg x 72 32 Meg x 72 MODULE BANDWIDTH 3.2 GB/s 3.2 GB/s 3.2 GB/s 3.2 GB/s MEMORY CLOCK/ DATA RATE 5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s LATENCY (CL - tRCD - tRP) 3-3-3 3-3-3 3-3-3 3-3-3
PART NUMBER MT9VDDT1672AG-40B__ MT9VDDT1672AY-40B__ MT9VDDT3272AG-40B__ MT9VDDT3272AY-40B__
NO TE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT3272AG-40BA1.
09005ae f80a43d 77 DDA9C16_32X72AG_C.fm - Rev. C 7/03 EN
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©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB (x72, ECC), PC3200 184-Pin DDR SDRAM DIMM
Table 3: Pin Assignment (184-Pin DIMM Front)
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS CK2# CK2 VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA S CL
Table 4:
Pin Assignment (184-Pin DIMM Back)
116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 VSS DQS17 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44 RAS# DQ45 VDDQ S0# NC DQS14 VSS DQ46 162 DQ47 163 NC 164 VDDQ 165 DQ52 166 DQ53 167 NC 168 VDD 169 DQS15 170 DQ54 171 DQ55 172 VDDQ 173 NC 174 DQ60 175 DQ61 176 VSS 177 DQS16 178 DQ62 179 DQ63 180 VDDQ 181 SA0 182 SA1 183 SA2 184 VDDSPD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
NO TE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 93 VSS 94 DQ4 95 DQ5 96 VDDQ 97 DQS9 98 DQ6 99 DQ7 100 VSS 101 NC 102 NC 103 NC 104 VDDQ 105 DQ12 106 DQ13 107 DQS10 108 VDD 109 DQ14 110 DQ15 111 NC 112 VDDQ 113 NC 114 DQ20 115 NC/A12
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1# VSS DQ10 DQ11 CKE0 VDDQ DQ16
Pin 115 is No Connect (128MB), and A12 (256MB).
Figure 2: 184-Pin DIMM Pinouts
FRONT VIEW
U10
U1
U2
U3
U4
U5
U6
U7
U8
U9
PIN 1
PIN 52 Indicates a VDD pin
PIN 53 Indicates a VSS pin
PIN 92
BACK VIEW
No Components This Side
PIN 184
09005ae f80a43d 77 DDA9C16_32X72AG_C.fm - Rev. C 7/03 EN
PIN 145
PIN 144
PIN 93
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc.
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128MB, 256MB (x72, ECC), PC3200 184-Pin DDR SDRAM DIMM
Table 5: Pin Descriptions
SYMBOL VREF WE#, CAS#, RAS# CK0, CK0#, CK1, CK1#, CK2, CK2# TYPE Input Input Input DESCRIPTION SSTL_2 reference voltage. Command Inputs: WE#, RAS#, and CAS# (along with S#) define the command being entered. Clocks: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE activates (HIGH) and deactivates (LOW) internal clock signals, device input buffers, and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE has been brought HIGH, it is an SSTL_2 input only. Chip Select: S# enables (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Bank Addresses: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: Sampled during the ACTIVE command (row-address) and READ/WRITE command (columnaddress, with A10 defining auto precharge) to select one location out of the memory array in the respective device device bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one device bank (A10 LOW) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. Data I/Os: Check bits. ECC, one-bit error detection and correction. Refer to Pin Assignment Tables on page 2 for pin number and symbol information PIN NUMBERS 1 63, 65, 154 16, 17, 75, 76, 137, 138
21
CKE0
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48, 115 (256MB), 118, 122, 125, 130, 141
A0-A11 (128MB) A0-A12 (256MB)
Input
92
SCL
Input
181, 182, 183 91
SA0-SA2 SDA
Input Input/Output
44, 45, 49, 51, 134, 135, 142, 144
CB0-CB7
Input/Output
09005ae f80a43d 77 DDA9C16_32X72AG_C.fm - Rev. C 7/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc.
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