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Part: DPL4519G
Category:
DSPs (Digital Signal Processors)
-> Audio DSPs
Description: Sound Processor For Digital And Analog Surround Systems
Company: Micronas Intermetall GmbH
Datasheet: Download DPL4519G datasheet File size : 104 kB
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PRELIMINARY DATA SHEET
MICRONAS
DPL 4519G Sound Processor for Digital and Analog Surround Systems
Edition Oct. 31, 2000 6251-512-1PD
MICRONAS
DPL 4519G
Contents Page 4 5 6 7 7 8 8 8 8 8 8 8 8 9 9 9 10 11 11 11 11 11 11 11 11 12 12 12 12 12 12 13 13 14 14 14 14 15 15 16 16 16 16 16 16 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.5.1. 2.6. 2.6.1. 2.6.1.1. 2.6.1.2. 2.6.1.3. 2.6.1.4. 2.6.2. 2.6.3. 2.6.3.1. 2.6.3.2. 2.6.3.3. 2.6.3.4. 2.6.4. 2.7. 2.7.1. 2.7.2. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. 2.9. 2.10. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. 3.1.5.1. 3.1.5.2. 3.1.5.3. 3.1.5.4. 3.2. Title Introduction Features of the DPL 4519G Application Fields of the DPL 4519G Functional Description Architecture of the DPL 4519G Family Preprocessing I2S Input Signals Selection of Internal Processed Surround Signals Source Selection and Output Channel Matrix Audio Baseband Processing Main and Aux Outputs Surround Processing Surround Processing Mode Decoder Matrix Surround Reproduction Center Modes Useful Combinations of Surround Processing Modes Examples Application Tips for using 3D-PANORAMA Sweet Spot Clipping Loudspeaker Requirements Cabinet Requirements Input and Output Levels for Dolby Surround Pro Logic SCART Signal Routing SCART Out Select Stand-by Mode I2S Bus Interfaces Synchronous I2S-Interface(s) Asynchronous I2S-Interface Multichannel I2S-Output Asynchronous Multichannel I2S-Input Digital Control I/O Pins Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Device and Subaddresses Internal Hardware Error Handling Description of CONTROL Register Protocol Description Proposals for General DPL 4519G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C Controlling
PRELIMINARY DATA SHEET
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
Contents, continued Page 16 16 19 19 21 21 33 34 34 34 35 35 37 40 43 45 47 47 48 48 48 49 50 50 51 52 53 54 56 58 58 61 61 62 64 Section 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.4. 3.5. 3.5.1. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 5. 5.1. 5.2. 6. Title DPL 4519G Programming Interface User Registers Overview Description of User Registers Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of Minimum Initialization Codes Micronas Dolby Digital chipset (with MAS 3528E) Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions (TA = 0 to 70 °C) General Recommended Operating Conditions Analog Input and Output Recommendations Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input and Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs and Outputs, AGNDC Power Supply Rejection Analog Performance Appendix A: Application Information Phase Relationship of Analog Outputs Application Circuit Data Sheet History
License Notice: "Dolby Pro Logic" and "Dolby Digital" are trademarks of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
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DPL 4519G
Sound Processor for Digital and Analog Surround Systems The hardware and software description in this document is valid for the DPL 4519G version A1 and following versions.
PRELIMINARY DATA SHEET
In an application together with the Dolby Digital decoder MAS 3528E, eight channels (left, right, surround left, surround right, center, subwoofer, Pro Logic encoded left, Pro Logic encoded right) are fed in and processed in the DPL 4519G. Similar to the multichannel I2S input interface, the DPL is provided with an 8-channel I2S output interface, which can be connected to a MSP 44x0G. Therefore all 8 channels can be routed to each output in both ICs. The baseband processing including e.g. balance, bass, treble, and loudness is performed at a fixed sample rate of 48 kHz. Fig. 11 shows a simplified functional block diagram of the DPL 4519G. The DPL 4519G is pin-compatible to members of the MSP 34xx family. This speeds up PCB development for customers using MSPs. The software interface of the DPL 4519G is also largely the same as for members of the MSP family. The ICs are produced in submicron CMOS technology and are available in PQFP80, PLQFP64 and in PSDIP64 packages.
1. Introduction The DPL 4519G processor is designed as part of the Micronas chip set for digital and analog Surround Systems i. e. Dolby Digital, MPEG 2 Audio, or Dolby ProLogic. The combination of MAS 3528E, DPL 4519G, and MSP 44x0G is a complete 5.1 channel Dolby Digital decoder and playback solution, while DPL 4519G and MSP 44x0G alone, represent a complete Dolby Surround Pro Logic system. The DPL 4519G receives its incoming data via highly flexible I2S interfaces. The three I2S input interfaces can be configured as three asynchronous I2S inputs or two synchronous and one asynchronous interface. In the latter case, the asynchronous interface allows reception of 2-8 channels with arbitrary sample rate ranging from 8 to 48 kHz. The synchronization is performed by means of an adaptive high-quality sample rate converter.
I2S 1
I2S Prescal e
Main Sound Processing
DAC
Mai n Subwoofer
I2S2
I2S
Source Select
I2S3
I2S (2..8-channel)
AUX Sound Processing
DAC
AUX
I2S (8-channel) DAC SCART Output Select SCART1
SCART1 SCART2 SCART3 SCART4 MO NO
ProLogic processing
SCART2
Fig. 11: Simplified block diagram of the DPL 4519G
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
1.1. Features of the DPL 4519G 8-channel asynchonous I2S input interface (multichannel mode) + 2 synchronous I2S input channels (e.g. for MSP and ADR) or 3 asynchronous two-channel I2S input interfaces Main and AUX channel with balance, bass, treble, loudness, volume 5-band graphic equalizer for Main channel Dolby Surround Pro Logic Adaptive Matrix Micronas Effect Matrix Micronas "3D-Panorama" virtualizer compliant to "Virtual Dolby Surround" technology Micronas Panorama sound mode (3D Surround sound via two loudspeakers) Noise Generator Spatial Effect for Surround 30-ms Surround delay Surround matrix control: Adaptive/Passive/Effect Center mode control: Normal/Phantom/Wide/Off Surround reproduction control: Rear speaker, Front speaker, Panorama, 3D-Panorama Two digital input/output pins controlled by I2C bus Fig. 12 shows a typical Dolby Digital application using DPL 4519G, MSP 4450G, and MAS 3528E.
Micronas
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