|
Details, datasheet, quote on part number:PUC303xA
| |
Datasheet text preview:
PRELIMINARY DATA SHEET
MICRONAS
PUC 303xA Programmable Universal Controller
Edition April 2, 2002 6251-565-1PD
MICRONAS
PUC 303xA
Contents Page Section Title
PRELIMINARY DATA SHEET
5
5 5
1.
1.1. 1.2.
Introduction
Features Application Overview
6
6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 8 11 12 13 15 15 15 16 19 19 19 20 20 20 20 21 21 21 24 26 26 26 27
2.
2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.1.7. 2.1.8. 2.1.9. 2.1.10. 2.1.11. 2.1.12. 2.1.13. 2.2. 2.2.1. 2.3. 2.3.1. 2.3.2. 2.4. 2.5. 2.5.1. 2.5.1.1. 2.5.1.2. 2.5.1.3. 2.5.1.4. 2.5.1.5. 2.5.2. 2.5.3. 2.5.3.1. 2.5.3.2. 2.5.4. 2.5.4.1. 2.5.4.2. 2.5.5. 2.6. 2.6.1. 2.6.1.1. 2.6.1.2.
Functional Description
Device Overview 64-MHz ARM7TDMI 48 + 8 kByte SRAM 256 kByte Embedded Flash Memory Protection Unit Power Management Unit 12-Mbit/s USB 1.1 Function Core 66 General-Purpose I/Os 5 x Synchronous Serial Port 2 x UARTs / IrDA 3 x Timer / Counters Watchdog Interrupt Controller Real Time Clock ARM7TDMI Processor and AHB/APB Buses Memory Map Clock Generation Clock Utilization Summary Phase-Locked Loop Device Power-on and Resets AHB Peripherals Flash Memory Flash Memory Map Flash Configuration Registers Flash Features Programmable Wait States Flash Programming and Erasing Security of Application Code SRAM Features General Overview Memory Protection Unit SRAM Remapping MPU Address Space USB Interface APB Peripherals Power Management Unit Power States Power Management Register Descriptions
2
April 2, 2002; 6251-565-1PD
Micronas
PRELIMINARY DATA SHEET
PUC 303xA
Contents, continued Page 37 37 37 38 38 40 48 48 48 50 65 65 66 66 67 68 70 79 80 80 80 81 81 82 83 89 89 89 89 89 98 101 101 101 102 102 102 106 106 106 106 106 107 107 107 107 Section 2.6.2. 2.6.2.1. 2.6.2.2. 2.6.2.3. 2.6.2.4. 2.6.2.5. 2.6.3. 2.6.3.1. 2.6.3.2. 2.6.3.3. 2.6.4. 2.6.4.1. 2.6.4.2. 2.6.4.3. 2.6.4.4. 2.6.4.5. 2.6.4.6. 2.6.4.7. 2.6.5. 2.6.5.1. 2.6.5.2. 2.6.5.3. 2.6.5.4. 2.6.5.5. 2.6.5.6. 2.6.6. 2.6.6.1. 2.6.6.2. 2.6.6.3. 2.6.6.4. 2.6.6.5. 2.6.7. 2.6.7.1. 2.6.7.2. 2.6.7.3. 2.6.7.4. 2.6.7.5. 2.6.8. 2.6.8.1. 2.6.8.2. 2.6.8.3. 2.6.8.4. 2.6.8.5. 2.6.8.6. 2.6.8.7. 2.6.8.8. Title Interrupt Controller Features Interrupt List General Overview Programming Guide Interrupt Controller Register Definitions UARTs Features UART Functions UART Register Map Synchronous Serial Ports SSP Peripheral Operation SSP Modes SSP Primary Modes SSP Secondary Modes Example SSP Communication Waveforms SSP Register Descriptions SSP Interrupt Logic Timers Features Description Initialization Modes of Operation Generation of Waveforms TTC Register Descriptions Real Time Clock Features Description Standby Mode Register Map and Formats Programming Instructions Watchdog Timer Features Description Watchdog Register Descriptions Watchdog Timer Reset Watchdog Timer Enable Sequence General Purpose I/O Module Features Description Bypass Mode Interrupts Signal Interface Initialization GPIO Address Map Programming Interface
Micronas
April 2, 2002; 6251-565-1PD
3
|
|
