Details, datasheet, quote on part number: M2V56S40AKT-5
PartM2V56S40AKT-5
CategoryMemory => DRAM => SDR SDRAM => 256 Mb
Description
CompanyMitsubishi Electronics America, Inc.
DatasheetDownload M2V56S40AKT-5 datasheet
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Features, Applications
MITSUBISHI LSIs SDRAM (Rev.1.1) Single Data Rate Aug '01
Some of contents are subject to change without notice.
DESCRIPTION

x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40AKT achieve very high speed data rate (-6), 166MHz(-5) and are suitable for main memory or graphic memory in computer systems.

FEATURES

- Single 3.3vą0.3V power supply - Max. Clock frequency -7:PC100<2-2-2> - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-8(x16) - LVTTL Interface - 10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch

VDD NC VDDQ NC DQ0 VSSQ NC VDDQ NC DQ1 VSSQ NC VDD NC /WE /CAS /RAS /CS A2 A3 VDD
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS A2 A3 VDD
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD NC LDQM /WE /CAS /RAS /CS A2 A3 VDD
CLK CKE /CS /RAS /CAS /WE DQ0-15 DQM, DQMU/L A0-12 BA0,1 Vdd VddQ Vss VssQ

Master Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O Output Disable / Write Mask Address Input Bank Address Input Power Supply Power Supply for Output Ground for Output

This rule is applied to only Synchronous DRAM family.

Power Grade L:Low Power, Space:Standard Speed Grade 7: 100MHz@CL2 Package Type KT: STSOP(II) Process Generation A:2nd. gen. Function Reserved for Future Use Organization 4: x16 SDRAM Data Rate Type S:Single Data Rate Density 56: 256M bits Interface V:LVTTL Memory Style (DRAM) Mitsubishi Main Designation


 

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