Details, datasheet, quote on part number: M2V56S40TP-7L
PartM2V56S40TP-7L
CategoryMemory => DRAM => SDR SDRAM => 256 Mb
Description
CompanyMitsubishi Electronics America, Inc.
DatasheetDownload M2V56S40TP-7L datasheet
  

 

Features, Applications
ry mina Preli SDRAM (Rev.1.5E) Single Data Rate Oct.2001
Some of contents are subject to change without notice.
DESCRIPTION

x 16-bit, synchronous DRAM, with LVTTL interface.All inputs and outputs are referenced to the rising edge of CLK.The M2V56S20/30/40TP achieve very high speed data rate , 166MHz(-5) and are suitable for main memory or graphic memory in computer systems.

FEATURES

-Single 3.3vą0.3V power supply -Max. Clock frequency -7:PC100 <2-2-2> Synchronous operation referenced to clock -Fully rising edge -Single Data Rate -4 bank operation controlled BA0, BA1 (Bank Address) -/CAS latency- 2/3 (programmable) -Burst length- 1/2/4/8/full page (programmable) -Burst type- sequential / interleave (programmable) -Random column access -Auto precharge / All bank precharge controlled A10 -8192 refresh cycles 64ms (4 banks concurrent refresh) -Auto refresh and Self refresh -Row address A0-12 / Column address A0-9(x8)/ A0-8(x16) -LVTTL Interface -400-mil, 54-pin Thin Small Outline Package (TSOPII) with 0.8mm lead pitch Max. Frequency 133MHz 100MHz Max. Frequency 133MHz 100MHz

Vdd NC VddQ NC DQ0 VssQ NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS A2 A3 Vdd
Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS A2 A3 Vdd
Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd LDQM /WE /CAS /RAS /CS A2 A3 Vdd

: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Output Disable / Write Mask : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output

This rule is applied to only Synchronous DRAM family.

7: 100MHz@CL2 Package Type TP: TSOP(II) Process Generation Function Reserved for Future Use Organization 3:x8, 4:x16 SDRAM Data Rate Type S:Single Data Rate Density 56: 256M bits Interface V:LVTTL Memory Style(DRAM) Mitsubishi Main Designation


 

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