|Category||Memory => SRAM => Async. SRAM => 256 Kb|
|Description||262144-bit (32768-word BY 8-bitcmos SRAM|
|Company||Mitsubishi Electronics America, Inc.|
|Datasheet||Download M5M5256 datasheet
|Cross ref.||Similar parts: M5M51257|
The is 262,144-bit CMOS static RAMs organized by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface. Especially the M5M5256DVP,RV are packaged a 28-pin thin small outline package.Two types of devices are available, M5M5256DVP(normal lead bend type package), M5M5256DRV(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.FEATURE
Type Access Power supply current time Active Stand-by (max) 150ns 20mA
Single +2.7~3.6V power supplyNo clocks, no refreshData-Hold on +2.0V power supplyDirectly TTL compatible : all inputs and outputsThree-state outputs : OR-tie capability/OE prevents data contention in the I/O busCommon Data I/OBattery backup capabilityLow stand-by current0.05µA(typ.)APPLICATION
The operation mode of the M5M5256DP,KP,FP,VP,RV is determined by a combination of the device control inputs /S, /W and /OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with the low level /S. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high level,the output stage in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting at a high level and /OE at a low level while /S are in an active state. When setting at a high level, the chip in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage in a high-impedance state, allowing OR-tie with other chips and memory expansion by /S. The power supply current is reduced as low as the stand-by current which is specified or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
/S /W /OE Mode Non selection Write Read DQ High-impedance DIN DOUT High-impedance Icc Stand-by Active25 26 ADDRESS INPUT BUFFER ROW DECODER WORD SENSE ANPLIFIER OUTPUT BUFFER X 8BIT
11 A9 WRITE CONTROL INPUT /W CHIP SELECT INPUT /S
8 DATA INPUT BUFFER COLUMN DECODER ADDRESS INPUT BUFFER
Symbol Parameter Supply voltage Vcc VO Pd Topr Tstg Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25°C Ratings -0.3*~4.6 -0.3*~Vcc+0.3
Symbol VIH VIL VOH1 VOH2 VOL II IO Parameter High-level input voltage Low-level input voltage High-level output voltage 1 IOH=-0.5mA
High-level output voltage 2 IOH=-0.05mA Low-level output voltage Input current Output current in off-state Active supply current
IOL=1mA VI=0~Vcc /S=VIH or /OE=VIH, VI/O=0~Vcc Min. /S0.2V, cycle Other >Vcc-0.2V 1MHz Output-open Min. cycle /S=VIL, other inputs=VIH or VIL Output-open Min. cycle /SVcc-0.2V, other inputs=0~Vcc /S=VIH,other inputs=0~Vcc Min. cycle 1MHz -VLL -VXL
Note 0: Direction for current flowing into IC is positive (no mark). 1: Typical value is one 25°C. 2: CI, CO are periodically sampled and are not 100% tested.
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