Details, datasheet, quote on part number: M5M5256
PartM5M5256
CategoryMemory => SRAM => Async. SRAM => 256 Kb
Description262144-bit (32768-word BY 8-bitcmos SRAM
CompanyMitsubishi Electronics America, Inc.
DatasheetDownload M5M5256 datasheet
Cross ref.Similar parts: M5M51257
Quote
Find where to buy
 
  

 

Features, Applications

DESCRIPTION

The is 262,144-bit CMOS static RAMs organized by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface. Especially the M5M5256DVP,RV are packaged a 28-pin thin small outline package.Two types of devices are available, M5M5256DVP(normal lead bend type package), M5M5256DRV(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.

FEATURE
Type Access Power supply current time Active Stand-by (max) 150ns 20mA

Single +2.7~3.6V power supplyNo clocks, no refreshData-Hold on +2.0V power supplyDirectly TTL compatible : all inputs and outputsThree-state outputs : OR-tie capability/OE prevents data contention in the I/O busCommon Data I/OBattery backup capabilityLow stand-by current0.05A(typ.)

APPLICATION

The operation mode of the M5M5256DP,KP,FP,VP,RV is determined by a combination of the device control inputs /S, /W and /OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with the low level /S. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high level,the output stage in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting at a high level and /OE at a low level while /S are in an active state. When setting at a high level, the chip in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage in a high-impedance state, allowing OR-tie with other chips and memory expansion by /S. The power supply current is reduced as low as the stand-by current which is specified or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.

/S /W /OE Mode Non selection Write Read DQ High-impedance DIN DOUT High-impedance Icc Stand-by Active

25 26 ADDRESS INPUT BUFFER ROW DECODER WORD SENSE ANPLIFIER OUTPUT BUFFER X 8BIT
11 A9 WRITE CONTROL INPUT /W CHIP SELECT INPUT /S
8 DATA INPUT BUFFER COLUMN DECODER ADDRESS INPUT BUFFER

Symbol Parameter Supply voltage Vcc VO Pd Topr Tstg Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25C Ratings -0.3*~4.6 -0.3*~Vcc+0.3

Symbol VIH VIL VOH1 VOH2 VOL II IO Parameter High-level input voltage Low-level input voltage High-level output voltage 1 IOH=-0.5mA

High-level output voltage 2 IOH=-0.05mA Low-level output voltage Input current Output current in off-state Active supply current

IOL=1mA VI=0~Vcc /S=VIH or /OE=VIH, VI/O=0~Vcc Min. /S0.2V, cycle Other >Vcc-0.2V 1MHz Output-open Min. cycle /S=VIL, other inputs=VIH or VIL Output-open Min. cycle /SVcc-0.2V, other inputs=0~Vcc /S=VIH,other inputs=0~Vcc Min. cycle 1MHz -VLL -VXL

Note 0: Direction for current flowing into IC is positive (no mark). 1: Typical value is one 25C. 2: CI, CO are periodically sampled and are not 100% tested.


 

Related products with the same datasheet
M5M5256B-10
M5M5256B-10L
M5M5256B-10LL
M5M5256B-12
M5M5256B-12L
M5M5256B-12LL
M5M5256B-15
M5M5256B-15L
M5M5256B-15LL
M5M5256B-70
M5M5256B-70L
M5M5256B-70LL
Some Part number from the same manufacture Mitsubishi Electronics America, Inc.
M5M5256B-10 262144-bit (32768-word BY 8-bitcmos SRAM
M5M5256CFP-12VLL 262144-bit ( 32768-word BY 8-bit ) CMOS Static RAM
M5M5256D 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D- 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-10VLL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-10VLL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-10VXL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-10VXL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-12VLL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-12VLL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-12VXL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-15VLL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-15VXL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-45LL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-45XL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-45XL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-55LL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-55LL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-55XL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-55XL- 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-70LL 262144-bit (32768-word BY 8-bit)cmos SRAM
Same catergory

APU8052 : 8-bit Micro Controller With 4/8kb ROM Emvedded.

GS72116A : . GS72116ATP/J/T/U SOJ, TSOP, FP-BGA, TQFP Commercial Temp Industrial Temp Fast access time: ns CMOS low power operation: mA at minimum cycle time Single 3.3 V power supply All inputs and outputs are TTL-compatible Byte control Fully static operation Industrial Temperature Option: to 85C Package line J: 400 mil, 44-pin SOJ package TP: 400 mil, 44-pin.

HS9-6664RH : Radiation Hardened 8k X 8 CMOS Prom. Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil is a radiation hardened 64K CMOS.

IS62LV256L : . High-speed access time: 20, 25 ns Automatic power-down when chip is deselected CMOS low power operation 255 mW (max.) operating 0.18 mW (max.) CMOS standby TTL compatible interface levels Single 3.3V power supply Fully static operation: no clock or refresh required Three-state outputs The ICSI is a very high-speed, low power, by 8-bit static RAM. It is fabricated.

K7Z167288B : DLW. = K7Z167288B 512Kx36 & 256Kx72-Bit Dlw(dobule Late Write) RAM ;; Organization = 256Kx72 ;; Operating Mode = - ;; VDD(V) = 1.8 ;; Access Time-tCD(ns) = - ;; Cycle Time(MHz) = 350 ;; I/o Voltage(V) = - ;; Package = 209BGA ;; Production Status = Engineering Sample(Q3,03) ;; Comments = -.

KM416C1000C : Asynchronous->5V FPM. 1m X 16bit CMOS Dynamic RAM With Fast Page Mode.

M15503EJ2V0DS00 : SRAM. 4M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT The by 16-bit, the by 32-bit and the by 36-bit synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The PD4442182-Y, PD4442322-Y and PD4442362-Y integrates unique synchronous peripheral circuitry, 2-bit burst counter.

M366S0823CTL : Unbuffered DIMM. = M366S0823CTL 8M X 64 Sdram Dimm Based on 8M X 8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 64 ;; Organization = 8Mx64 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = 10 ;; #of Pin = 168 ;; Power = C ;; Component Composition = (8Mx8)x8+EEPROM ;; Production Status = Eol ;; Comments = PC66.

MWS5101 : SRAM. 256-Word X 4-Bit Lsi Static RAM. Industry Standard Pinout Very Low Operating Current. 8mA at VDD = 5V and Cycle Time = 1s Two Chip Select Inputs Simple Memory Expansion Memory Retention for Standby. 2V (Min) Battery Voltage Output Disable for Common I/O Systems Three-State Data Output for Bus Oriented Systems Separate Data Inputs and Outputs TTL Compatible (MWS5101A) MWS5101 PACKAGE.

MX23L12811 : 128M, 16Mx8/8Mx16. x 16) MASK ROM WITH PAGE MODE (SOP ONLY) Bit organization x 16 (word mode) Fast access time - Random access: 90ns (max.) - Page access: 25ns (max.) Page size - 8 words per page Current - Standby:15uA Supply voltage ~ 3.6V Package - 44 pin SOP (500mil) Temperature 0~70 C Symbol CE OE VCC VSS NC Pin Function Address Inputs Data Outputs Chip Enable Input.

NT256D64SH8BAGM-6K : 200 pin SODIMM. 32M X 64, DS, 2.5V, 16 X 16, (8), 2, PC2700, PC2100. / PC2100 Unbuffered DDR SO-DIMM 200pin Unbuffered DDR SO-DIMM Based DDR333/266 16Mx16 SDRAM JEDEC Standard 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) 32Mx64 Double Unbuffered DDR SO-DIMM based on 16Mx16 DDR SDRAM. Performance: PC2700 PC2100 Speed Sort DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ Burst Frequency -6K -75B.

SEA01 : PCMCIA SRAM Cards. Density = 32KB-512KB ;; Memory Device = 256Kb,1,2,&4Mb ;; Organization = x8 ;; Speed (ns) = 150 ;; Volt = 5 ;;.

W49L401 : 256K-16.

WED416S8030A : Industrial SDRAM. Organization = 2Mx16x4 ;; Speed MHZ = 83-100 ;; Volt = 3.3 ;; Package = 54 Tsop ii ;; Temp = C,i ;;.

M366S3253JUS-C7A : 32M X 64 DDR DRAM, DMA168. s: Memory Category: DRAM Chip ; Density: 2147484 kbits ; Number of Words: 32000 k ; Bits per Word: 64 bits ; Package Type: HALOGEN FREE AND ROHS COMPLIANT, DIMM-168 ; Pins: 168 ; Supply Voltage: 3.3V ; Operating Temperature: 0 to 70 C (32 to 158 F).

72T20108L10BBG : 64K X 20 OTHER FIFO, 4.5 ns, PBGA208. s: Memory Category: FIFO ; Density: 1311 kbits ; Number of Words: 64 k ; Bits per Word: 20 bits ; Package Type: BGA, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208 ; Pins: 208 ; Logic Family: CMOS ; Supply Voltage: 2.5V ; Access Time: 4.5 ns ; Cycle Time: 10 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).

 
0-C     D-L     M-R     S-Z