Details, datasheet, quote on part number: M5M5256D-55XL-
PartM5M5256D-55XL-
CategoryMemory
Description262144-bit (32768-word BY 8-bit) CMOS Static RAM
CompanyMitsubishi Electronics America, Inc.
DatasheetDownload M5M5256D-55XL- datasheet
  

 

Features, Applications

DESCRIPTION

The is 262,144-bit CMOS static RAMs organized by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface. Especially the M5M5256DVP,RV are packaged a 28-pin thin small outline package.Two types of devices are available, M5M5256DVP(normal lead bend type package), M5M5256DRV(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.

FEATURE
Type Access Power supply current time Active Stand-by (max) 70ns 55mA

Single +5V power supplyNo clocks, no refreshData-Hold on +2.0V power supplyDirectly TTL compatible : all inputs and outputsThree-state outputs : OR-tie capability/OE prevents data contention in the I/O busCommon Data I/OBattery backup capabilityLow stand-by current0.05A(typ.)

APPLICATION

The operation mode of the M5M5256DP,KP,FP,VP,RV is determined by a combination of the device control inputs /S, /W and /OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with the low level /S. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high level,the output stage in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting at a high level and /OE at a low level while /S are in an active state. When setting at a high level, the chip in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage in a high-impedance state, allowing OR-tie with other chips and memory expansion by /S. The power supply current is reduced as low as the stand-by current which is specified or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.

/S /W /OE Mode Non selection Write Read DQ High-impedance DIN DOUT High-impedance Icc Stand-by Active

25 26 ADDRESS INPUT BUFFER ROW DECODER WORD SENSE ANPLIFIER OUTPUT BUFFER X 8BIT
11 A9 WRITE CONTROL INPUT /W CHIP SELECT INPUT /S
8 DATA INPUT BUFFER COLUMN DECODER ADDRESS INPUT BUFFER

Symbol Parameter Supply voltage Vcc VO Pd Topr Tstg Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25C Ratings -0.3*~7.0 -0.3*~Vcc+0.3

Symbol VIH VIL VOH1 VOH2 VOL II IO Parameter High-level input voltage Low-level input voltage High-level output voltage 1 High-level output voltage 2 Low-level output voltage Input current Output current in off-state Active supply current

IOL=2mA VI=0~Vcc /S=VIH or /OE=VIH, 45ns /S0.2V, Other >Vcc-0.2V 55ns Output-open Min. cycle 70ns /S=VIL, other inputs=VIH or VIL Output-open Min. cycle /SVcc-0.2V, other inputs=0~Vcc /S=VIH,other 55ns 70ns -LL -XL

Note 0: Direction for current flowing into IC is positive (no mark). 1: Typical value is one 25C. 2: CI, CO are periodically sampled and are not 100% tested.


 

Related products with the same datasheet
M5M5256D-45XL-I
M5M5256D-55LL-I
M5M5256D-70LL-I
Some Part number from the same manufacture Mitsubishi Electronics America, Inc.
M5M5256D-70LL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-70LL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-70VLL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-70VLL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-70VXL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-70VXL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-70XL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-85VLL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256D-85VXL 262144-bit (32768-word BY 8-bit)cmos SRAM
M5M5256D-85VXL-I 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256DFP Lsis: 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256DFP-55LL 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256DFP-55LL-I
M5M5256DFP-55LL-W
M5M5256DFP-55XL-I
M5M5256DFP-55XL-W
M5M5256DFP-70LL-I
M5M5256DFP-70LL-W
M5M5256DFP-70VLL Lsis: 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256DFP-70XL 262144-bit (32768-word BY 8-bit) CMOS Static RAM
M5M5256DFP-70XL-I

M30610ECFP :

M38021M1DXXXFS : RAM Size: 256bytes; Single-chip 8-bit CMOS Microcomputer

M38066E9-XXXFP : RAM Size: 896bytes; Single-chip 8-bit CMOS Microcomputer

M38067M8AXXXGP : RAM Size: 1024bytes; Single-chip 8-bit CMOS Microcomputer

M38190E6-XXXFP : RAM Size: 192bytes; Single-chip 8-bit CMOS Microcomputer

M38194MB-XXXFS : RAM Size: 640bytes; Single-chip 8-bit CMOS Microcomputer

M38253M4DXXXGP : RAM Size: 512 Bytes; Single-chip 8-bit CMOS Microcomputer

M38256M3DXXXGP : RAM Size: 896 Bytes; Single-chip 8-bit CMOS Microcomputer

M38258E1-GP : RAM Size: 1536 Bytes; Single-chip 8-bit CMOS Microcomputer

M38749MCT-XXXGP : Single-chip 8-bit CMOS Microcomputer

PD8XX2 : Ingaasp- Avalanche Photo Diode

DSSV-401M : DIA Surge Suppressor (dss)

 
0-C     D-L     M-R     S-Z