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Part: M5M5408BTP-55L
Category:
Memory
-> SRAM
-> Async. SRAM
-> 4 Mb
Description: 4194304-bit (524288-word BY 8-bit) CMOS Static RAM
Company: Mitsubishi Electronics America, Inc.
Datasheet: Download M5M5408BTP-55L datasheet File size : 484 kB
Request For quote: Find where to buy M5M5408BTP-55L
Datasheet text preview:
revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5408B is a family of 4-Mbit static RAMs organized as 524,288-words by 8-bit, fabricated by Mitsubishi's highperformance 0.25µm CMOS technology. The M5M5408B is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5408B is packaged in 32-pin plastic SOP and 32-pin plastic TSOP packages. Two types of TSOPs are available , M5M5408BTP (normal-lead-bend TSOP) and M5M5408BRT (reverse-lead-bend TSOP). These two types TSOPs are suitable for a surface mounting on double-sided printed circuit boards. From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below.
FEATURES
· Single +5V power supply · Small stand-by current: 0.4µA(3V,typ.) · No clocks, No refresh · Data retention supply voltage=2.0V to 5.5V · All inputs and outputs are TTL compatible. · Easy memory expansion by S · Common Data I/O · Three-state outputs: OR-tie capability · OE prevents data contention in the I/O bus · Process technology: 0.25µm CMOS · Package: M5M5408BFP: 32 pin 525 mil SOP M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
PART NAME TABLE
Version, Operating temperature Part name (## stands for "FP","TP","RT") M5M5408B## -55L
Power Supply
Access time
Stand-by current Icc(PD), Vcc=3.0V typical * Ratings (max.) 25°C --70°C 50µA 85°C ---
max.
55ns
Active current Icc1 (5.0V, typ.)
Standard 0 ~ +70°C
M5M5408B## -70L M5M5408B## -55H
5.0V
70ns 55ns
5.0V M5M5408B## -70H M5M5408B## -55LW 5.0V 70ns 55ns
0.4µA
15µA
---
--70ns 55ns
---
100µA
50mA (10MHz) 25mA (1MHz)
W-version -20 ~ +85°C
M5M5408B## -70LW M5M5408B## -55HW 5.0V M5M5408B## -70HW M5M5408B## -55LI 5.0V
0.4µA 70ns 55ns --70ns 55ns
---
30µA
---
100µA
I-version -40 ~ +85°C
M5M5408B## -70LI M5M5408B## -55HI 5.0V M5M5408B## -70HI
0.4µA 70ns
---
30µA
* "typical" parameter is sampled, not 100% tested.
MITSUBISHI ELECTRIC
1
revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
PIN CONFIGURATION (TOP VIEW)
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 (0V) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC (5V) A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4
Outline
32P2M-A (FP) 32P3Y-H (TP)
(5V) VCC
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND (0V)
Outline
32P3Y-J (RT)
MITSUBISHI ELECTRIC
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5408BFP,TP,RT is organized as 524,288-words by 8-bit. These devices operate on a single +5.0V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. A write operation is executed during the S low and W low overlap time. The address(A0~A18) must be set up before the write cycle A read operation is executed by setting W at a high level and OE at a low level while S are in an active state(S=L). When setting S at a high level, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. The power supply current is reduced as low as 0.4µA(25°C, typical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S H L L L W X L H H OE X X L H Mode Non selection Write Read Read DQ High-impedance Data input (D) Data output (Q) High-impedance Icc Standby Active Active Active
Pin A0 ~ A18 S W OE Vcc GND
Function Address input Chip select input Write control input Output inable input Power supply Ground supply
DQ1 ~ DQ8 Data input / output
BLOCK DIAGRAM
M5M5408B FP/TP/RT M5M5408B FP/TP/RT
13 14
A4 A5 A6 A7 A12 A14 A16 A17 A18 A15 A10 A11 A9 A8 A13
8 7 6 5 4 3 2 30 1 31
MEMORY ARRAY 524288 WORDS x 8 BITS
15 17 18 19 20 21
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
23 25 26 27 28 29 22 24
CLOCK GENERATOR
W S OE VCC
(5V)
A0 A1 A2 A3
12 11 10 9
32
16
GND
(0V)
MITSUBISHI ELECTRIC
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