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Part: M5M54R01J-15
Category:
Description: 4194304-bit ( 4194304-word BY 1-bit ) CMOS Static RAM
Company: Mitsubishi Electronics America, Inc.
Datasheet: Download M5M54R01J-15 datasheet File size : 484 kB
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Datasheet text preview:
MITSUBISHI LSIs
1998.11.30 Ver.B
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
PIN CONFIGURATION (TOP VIEW)
DESCRIPTION
The M5M54R01AJ is a family of 4194304-word by 1-bit static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well.
address inputs chip select input
A0 A1 A2 A3 A4 A5 S D W A6 A7 A8 A9 A10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
FEATURES
·Fast access time M5M54R01AJ-12 ... 12ns(max) M5M54R01AJ-15 ... 15ns(max)
(3.3V) VCC (0V) GND
data inputs write control input address inputs
·Single +3.3V power supply ·Fully static operation : No clocks, No refresh ·Easy memory expansion by S ·Three-state outputs : OR-tie capability ·OE prevents data contention in the I/O bus ·Directly TTL compatible : All inputs and outputs
A21 A20 address A19 inputs A18 A17 A16 output enable OE input GND (0V) VCC (3.3V) data outputs Q A15 A14 address A13 inputs A12 A11 B1/B4 byte control input
Outline
32P0K
APPLICATION
High-speed memory units
PACKAGE
M5M54R01AJ : 32pin 400mil SOJ
BLOCK DIAGRAM
A0 A1 A2 A3
address inputs
1 2 3 4 5 6
MEMORY ARRAY 1024 ROWS 4096 COLUMNS
A4 A5
23 Q outputs
data
A6 12 A7 13 A8 14 A9 15 S 7
COLUMN I/O CIRCUITS C COLUMN OLUMN ADDRESS ADDRESS DECODERS DECODERS COLUMN INPUT BUFFERS
10 D inputs/ 8 24 VCC (3.3V)
data
W
11
OE 26 B1/B4 17 16 18 19 20 21 22 27 28 29 30 31 32 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
address inputs
9 GND (0V) 25
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M54R01AJ is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a non-selectable mode in which both reading and writing are disable. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. The RAM works with an organization of 4194304-word by 1bit, when B1/B4 is low of floating. And an organization of 1048576-word by 4bit is also obtained for reducing the test time,when B1/B4 is high. The pin configuration and function is as same as M5M54R04AJ.
FUNCTION TABLE
B1/B4 L L L L S H L L L W X L H H OE X X L H Mode Non selection Write Read D High-impedance Din High-impedance High-impedance Q High-impedance High-impedance Dout High-impedance Icc Stand by Active Active Active
ABSOLUTE MAXIMUM RATINGS
Symbol V cc VI VO Pd T opr T stg
* Pulse
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature
Conditions With respect to GND
Ratings - 2.0 * 4.6 ~ *~ VCC+0.5 - 2.0 - 2.0*~ VCC 1000 0 ~ 70 - 10 ~ 85 - 65 ~ 150
+10% - 5%
Unit V V V mW °C °C °C
Ta=25°C
Tstg(bias) Storage temperature(bias) Storage temperature
width3ns, In case of DC: - 0.5V
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V
Symbol VIH VIL VOH VOL II I OZ Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Condition
,unless otherwise noted)
Limits Min 2.0 2.4 0.4 2 2 Typ Max Vcc+0.3 0.8 Unit V V V V uA uA
I OH = - 4mA IOL = 8mA VI= 0 ~ Vcc VI(S)=VIH Output current in off-state VI/O= 0 ~ Vcc Active supply current (TTL level) VI(S)=VIL other inpus=VIH or VIL Output-open(duty 100%) AC DC 12ns cycle 15ns cycle
180 160 90 mA
I CC1
I CC2
Stand by current (TTL level)
VI(S)=VIH VI(S)=Vcc0.2V other inputs VI0.2V or VI Vcc - 0.2V
AC DC
12ns cycle 15ns cycle
70 60 40 10 mA mA
I CC3
Stand by current
Note 1: Direction for current flowing into an IC is positive (no mark).
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
CAPACITANCE (Ta=0~70°C, Vcc=3.3V
Symbol CI CO Parameter Input capacitance Output capacitance
+10% -5%
,unless otherwise noted)
Test Condition Min Limit Typ Max 8 8 Unit pF pF
V I =GND, V I =25mVrms,f=1MHz V O=GND, V O=25mVrms,f=1MHz
Note 2: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V (1)MEASUREMENT CONDITION
+10% -5%
,unless otherwise noted)
Input pulse levels ... VIH=3.0V, VIL=0.0V Input rise and fall time .... 3ns Input timing reference levels ...... VIH=1.5V, VIL=1.5V Output timing reference levels ........ VOH =1.5V, VOL=1.5V Output loads ........ Fig.1,Fig.2
5.0V OUTPUT Z0=50 DQ RL=50 VL=1.5V DQ 255 480 5pF (including scope and JIG)
Fig.1 Output load
Fig.2 Output load for ten , t dis
MITSUBISHI ELECTRIC
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