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Details, datasheet, quote on part number:V29C31004B-90T
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Datasheet text preview:
MOSEL VITELIC
V29C31004T/V29C31004B 4 MEGABIT (524,288 x 8 BIT) 3.3 VOLT CMOS FLASH MEMORY
Description
PRELIMINARY
Features
s s s s s s 512Kx8-bit Organization Address Access Time: 90, 120 ns Single 3.3V ± 0.3 Power Supply Sector Erase Mode Operation 16KB Boot Block (lockable) 1K bytes per Sector, 512 Sectors Sector-Erase Cycle Time: 10ms (Max) Byte-Write Cycle Time: 60µs (Max) Minimum 10,000 Erase-Program Cycles Low power dissipation Active Read Current: 16mA (Typ) Active Program Current: 30mA (Typ) Standby Current: 50µA (Max) Hardware Data Protection Low VCC Program Inhibit Below 2.5V Self-timed write/erase operations with end-of-cycle detection DATA Polling Toggle Bit CMOS and TTL Interface Available in two versions V29C31004T (Top Boot Block) V29C31004B (Bottom Boot Block) Packages: 32-pin TSOP-I 32-pin PLCC
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s s s
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The V29C31004T/V29C31004B is a high speed 524,288 x 8 bit CMOS flash memory. Writing or erasing the device is done with a single 3.3 Volt power supply. The device has separate chip enable C E, write enable WE, and output enable OE controls to eliminate bus contention. The V29C31004T/V29C31004B offers a combin a t i o n of: Boot Block with Sector Erase/Write Mode. The end of write/erase cycle is detected by DATA Polling of I/O7 or by the Toggle Bit I/O6. T h e V29C31004T/V29C31004B features a sector erase operation which allows each sector to b e erased and reprogrammed without affecting d a t a stored in other sectors. The device also supports full chip erase. Boot block architecture enables the device to boot from a protected sector located either at the top (V29C31004T) or the bottom (V29C31004B). A l l inputs and outputs are CMOS and TTL compatible. T h e V29C31004T/V29C31004B is ideal for applications that require updatable code and data storage.
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Device Usage Chart
Operating Temperature Range 0°C to 70°C Package Outline T · J · Access Time (ns) 90 · 120 · Temperature Mark Blank
V29C31004T/V29C31004B Rev. 0.3 October 2000
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MOSEL VITELIC
V 29 C 31 004 T
V29C31004T/V29C31004B
OPERATING VOLTAGE 31: 3.3V
DEVICE
SPEED T = TSOP-I J = PLCC
PKG.
TEMP. BLANK (0°C TO 70°C)
31004-01
BOOT BLOCK LOCATION T: TOP B: BOTTOM
90: 90ns 12: 120ns
Pin Configurations
VCC WE A12 A15 A16 A18 A17
4
3
2
1 32 31 30 29 28 27 26 25 24 23 22 21
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A14 A13 A8 A9 A11 OE A10 CE I/O7
32 Pin PLCC Top View
A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin TSOP I Standard Pinout Top View
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
51004-04
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
I/O1
I/O2
I/O3
I/O4
I/O5
GND
I/O6
51004-03
Pin Names
A0A18 I/O0I/O7 CE OE WE VCC GND NC Address Inputs Data Input/Output Chip Enable Output Enable Write Enable 5V ± 10% Power Supply Ground No Connect
V29C31004T/V29C31004B Rev. 0.3 October 2000
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MOSEL VITELIC
Functional Block Diagram
V29C31004T/V29C31004B
X-Decoder
4,194,304 Bit Memory Cell Array
A0A18
Address buffer & latches
Y-Decoder
CE OE WE
Control Logic
I/O Buffer & Data Latches
I/O0I/O7
51004-07
Capacitance (1,2)
Symbol
CIN COUT CIN2
Parameter
Input Capacitance Output Capacitance Control Pin Capacitance
Test Setup
VIN = 0 VOUT = 0 VIN = 0
Typ.
6 8 8
Max.
8 12 10
Units
pF pF pF
NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25°C, VCC = 5V ± 10%, f = 1 MHz.
Latch Up Characteristics(1)
Parameter
Input Voltage with Respect to GND on A9, OE Input Voltage with Respect to GND on I/O, address or control pins VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 3.3V, one pin at a time.
Min.
-1 -1 -100
Max.
+13 VCC + 1 +100
Unit
V V mA
AC Test Load
+3.3 V IN3064 or Equivalent Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 k IN3064 or Equivalent IN3064 or Equivalent
31004-08
2.7 k
V29C31004T/V29C31004B Rev. 0.3 October 2000
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