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Details, datasheet, quote on part number:V29LC51002P90
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Datasheet text preview:
MOSEL VITELIC
V29LC51002 2 MEGABIT (262,144 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
Description
PRELIMINARY
Features
s s s s s 256Kx8-bit Organization Address Access Time: 90 ns Single 5V ± 10% Power Supply Sector Erase Mode Operation 512 bytes per Sector, 512 Sectors Sector-Erase Cycle Time: 10ms (Max) Byte-Write Cycle Time: 30µs (Max) Minimum 1,000 Erase-Program Cycles Low power dissipation Active Read Current: 20mA (Typ) Active Program Current: 30mA (Typ) Standby Current: 100µA (Max) Low VCC Program Inhibit Below 3.5V CMOS and TTL Interface Packages: 32-pin Plastic DIP 32-pin PLCC
s s
The V29LC51002 is a high speed 262,144 x 8 bit CMOS flash memory. Writing or erasing the device i s done with a single 5 Volt power supply. The device has separate chip enable CE, write enable WE, and output enable OE controls to eliminate bus contention. T h e V29LC51002 features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase.
s s s
Device Usage Chart
Operating Temperature Range 0°C to 70°C Package Outline P · J · Access Time (ns) 90 · Temperature Mark Blank
V29LC51002 Rev. 0.5 October 2000
1
MOSEL VITELIC
V 29 LC 51 002
V29LC51002
OPERATING VOLTAGE 51: 5V
DEVICE 90: 90ns
SPEED
PKG. P = PDIP J = PLCC
C51002-01
Pin Configurations
VC C WE A12 A15 A16 NC
N/C A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 32-Pin PDIP 26 Top View 25 24 23 22 21 20 19 18 17
51002-02
VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
4
3
2
1 32 31 30 29 28 27 26 25 24 23 22 21
A17
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A14 A13 A8 A9 A11 OE A10 CE I/O7
32 Pin PLCC Top View
I/O1
I/O2
I/O3
I/O4
I/O5
GND
I/O6
51002-03
Pin Names
A0A17 I/O0I/O7 CE OE WE VCC GND NC Address Inputs Data Input/Output Chip Enable Output Enable Write Enable 5V ± 10% Power Supply Ground No Connect
V29LC51002 Rev. 0.5 October 2000
2
MOSEL VITELIC
Functional Block Diagram
2,097,152 Bit Memory Cell Array
V29LC51002
X-Decoder
A0A17
Address buffer & latches
Y-Decoder
CE OE WE
Control Logic
I/O Buffer & Data Latches
I/O0I/O7
51002-07
Capacitance (1,2)
Symbol
CIN COUT CIN2
Parameter
Input Capacitance Output Capacitance Control Pin Capacitance
Test Setup
VIN = 0 VOUT = 0 VIN = 0
Typ.
6 8 8
Max.
8 12 10
Units
pF pF pF
NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25°C, VCC = 5V ± 10%, f = 1 MHz.
Latch Up Characteristics(1)
Parameter
Input Voltage with Respect to GND on A9, OE Input Voltage with Respect to GND on I/O, address or control pins VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time.
Min.
-1 -1 -100
Max.
+13 VCC + 1 +100
Unit
V V mA
AC Test Load
+5.0 V IN3064 or Equivalent Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 k IN3064 or Equivalent IN3064 or Equivalent
51002-08
2.7 k
V29LC51002 Rev. 0.5 October 2000
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