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Details, datasheet, quote on part number:V53C16125HT45
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Datasheet text preview:
MOSEL VITELIC
V53C16125H HIGH PERFORMANCE 128K X 16 BIT FAST PAGE MODE CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
40
40 ns 20 ns 23 ns 75 ns
45
45 ns 22 ns 25 ns 80 ns
50
50 ns 24 ns 28 ns 90 ns
60
60 ns 30 ns 40 ns 110 ns
Features
s 256K x 16-bit 1.6 s Fast Page Mode for a sustained data rate of 44 MHz s RAS access time: 40, 45, 50, 60ns s Dual CAS Inputs s Low Power Dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh s Refresh Interval: 256 cycles/8 ms s Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages s Single +5V±10% Power Supply s TTL Interface
Description
The V53C16125H is a 131,072 x 16 bit high p e r f o r m a n c e CMOS dynamic random access memory. The V53C16125H offers Fast Page mode w i t h dual CAS inputs. The V53C16125H has asymmetric address, 8-bit row and 9-bit column. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256 x 16 bits, within a page, with cycle times as short as 19ns. T h e V53C16125H is ideally suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating Temperature Range
0°C to 70 °C
Package Outline K
·
Access Time (ns) 40 45
·
Power 60
·
T
·
50
·
Std.
·
Temperature Mark
Blank
V53C16125H Rev. 1.6 September 1998
1
MOSEL VITELIC
V 5 3 C 16 1 2 5 H
V53C16125H
FAMILY
DEVICE
PKG. SPEED ( t RAC)
TEMP. PWR. BLANK (0¡C to 70¡C) BLANK (NORMAL)
Description
SOJ TSOP-II
Pkg.
K T
Pin Count
40 40/44L
K (SOJ) T (TSOP-II) 40 45 50 60
(40 ns) (45 ns) (50 ns) (60 ns)
16125H-01
40-Pin Plastic SOJ PIN CONFIGURATION Top View
Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC A0 A1 A2 A3 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
16125H-02
40/44L-Pin Plastic TSOP-II PIN CONFIGURATION Top View
Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8
1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35
Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss
Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9
Pin Names
A0A8 RAS UCAS Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect
LCAS
NC NC WE RAS NC A0 A1 A2 A3 Vcc
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
16125H-03
NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss
WE OE I/O1I/O16 VCC VSS NC
Absolute Maximum Ratings*
Ambient Temperature Under Bias ........ 10°C to +80°C Storage Temperature (plastic) ..... 55°C to +125°C Voltage Relative to VSS ........1.0 V to +7.0 V Data Output Current .... 50 mA Power Dissipation ......... 1.0 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
Capacitance*
TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. 3 4 5 Max. 4 5 7 Unit pF pF pF
*Note: Capacitance is sampled and not 100% tested
V53C16125H Rev. 1.6 September 1998
2
MOSEL VITELIC
Block Diagram
128K x 16
OE WE UCAS LCAS RAS
V53C16125H
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC VSS
DATA I/O BUS COLUMN DECODERS
Y0Y8
I/O 1 I/O2 I/O3 I/O4 I/O 5 I/O6 I/O7
SENSE AMPLIFIERS REFRESH COUNTER
512 x 16 9 A0 A1
I/O BUFFER
I/O8 I/O 9 I/O10 I/O11
ADDRESS BUFFERS AND PREDECODERS
ROW DECODERS
X0X7
256
· · ·
A7 A8
MEMORY ARRAY
I/O12 I/O 13 I/O14 I/O15 I/O16
256 x 512 x 16
16125H-04
V53C16125H Rev. 1.6 September 1998
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