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Details, datasheet, quote on part number:V53C364405A
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Datasheet text preview:
MOSEL VITELIC
V53C364405A 3.3 VOLT 16M X 4 EDO PAGE MODE CMOS DYNAMIC RAM
V53C364405A
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
40
40 ns 20 ns 16 ns 69 ns
50
50 ns 25 ns 20 ns 84 ns
60
60 ns 30 ns 25 ns 104 ns
s 16M x 4-bit organization s EDO Page Mode for a sustained data rate of 63 MHz s RAS access time: 40, 50, 60 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh s Self Refresh (L-version only) s Refresh Interval: 8192 cycles/128 ms s Available in 32-pin 400 mil SOJ, and 32-pin 400 mil TSOP-II s Single +3.3 V ±0.3 V Power Supply s LV-TTL Interface
Description
The V53C364405A is a 16,777,216 x 4 bit highperformance CMOS dynamic random access memory. The V53C364405A offers Page mode operation with Extended Data Output. The V53C364405A has an address, 13-bit row and 11-bit column. All inputs are LV-TTL compatible. EDO Page Mode operation allows random access up to 2048 x 4 bits, within a page, with cycle times as short as 16 ns. These features make the V53C364405A ideally suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating Temperature Range
0°C to 70°C
Package Outline K
·
Access Time (ns) 40
·
Power 60
·
T
·
50
·
Std.
·
L
·
Temperature Mark
Blank
V53C364405A Rev. 1.2 June 1998
1
MOSEL VITELIC
32 Pin Plastic SOJ /TSOP-II PIN CONFIGURATION Top View
VCC I/O1 I/O2 NC NC NC NC RE W AS A
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
6540500 02
V53C364405A
Pin Names
A0A12 RAS Row, Column Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +3.3V Supply 0V Supply No Connect
VSS I/O4 I/O3 NC NC NC O CAS AE
12
CAS WE OE I/O1I/O4 VCC VSS NC
A1 A2 A3 A4 A5 VCC
A11 A10 A9 A8 A7 A6 VSS
Description SOJ TSOP-II
Pkg. K T
Pin Count 32 32
V53C364405A Rev. 1.2 June 1998
2
MOSEL VITELIC
Operating temperature range .........0 to 70 °C Storage temperature range ...... -55 to 150 °C Soldering temperature ..........260 °C Soldering time.........10 s Input/output voltage .... -0.5 to min (VCC+0.5, 4.6) V Power supply voltage ......-0.5V to 4.6 V Power dissipation ......... 1.0 W Data out current (short circuit) .... 50 mA
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V53C364405A
Capacitance*
TA = 25°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V, f = 1 Mhz
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Min. -- -- -- Max. 5 7 7 Unit pF pF pF
Absolute Maximum Ratings*
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
16M x 4
I/O1 I/O2 I/O3 I/O4
Data In Buffer WE CAS 4
Data Out Buffer 4
OE
No. 2 Clock Generator
11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Column Address Buffers (11)
11
Column Decoder
Refresh Controller Sense Amplifier I/O Gating Refresh Counter (13) 13 13 Row Address Buffers (13) 13 Row Decoder 8192 Memory Array 8192 x 2048 x 4 2048 x4
4
RAS
No. 1 Clock Generator
V53C364405A Rev. 1.2 June 1998
3
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