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Details, datasheet, quote on part number:V54C316162V-55
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Datasheet text preview:
V54C316162V 200/183/166/143 MHz 3.3 VOLT, 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
s JEDEC Standard 3.3V Power Supply s The V54C316162V is ideally suited for high performance graphics peripheral applications s Single Pulsed RAS Interface s Programmable CAS Latency: 2, 3 s All Inputs are sampled at the positive going edge of clock s Programmable W rap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and Full Page for Sequential and 1, 2, 4, 8 for Interleave s UDQM & LDQM for byte masking s Auto & Self Refresh s 4K Refresh Cycles/64 ms s Burst R ead with Single W rite Operation
CILETIV LESOM
V 54C3 16162V
Clock Frequency ( tCK) Latency Cycle Time (tC K) Access Time (tAC )
-5
200 3 5 5
-55
183 3 5.5 5.3
-6
166 3 6 5.5
-7
143 3 7 5.5
Un i t
MHz clocks ns ns
Features
Description
The V54C316162V is a 16,777,216 bits synchronous hi gh dat a r at e DRA M organi z ed as 2 x 524,288 words by 16 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation.
V54C316162V Rev.2.9 September 2001
1
V54C316162V
Pin Names
CLK CKE CS Clock Input Clock Enable Chip Select Row Addr ess Strobe Column A ddress Strobe Write E nable A ddress Inputs B ank Select Data Input/Output Data Mask P ower (+3.3V) Ground P ower for I/O's (+3.3V) Ground for I/O's Not connected
CILETIV LESOM
50 Pin Plastic TSOP-II PIN CON FIGURATION Top View
VCC I/O1 I/O2 VSSQ I/O3 I/O4 VCCQ I/O5 I/O6 VSSQ I/O7 I/O8 VCCQ LDQM WE CAS RAS CS BA A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
V54C316162V-01
VSS I/O16 I/O15 VSSQ I/O14 I/O13 VCCQ I/O12 I/O11 VSSQ I/O10 I/O9 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS
RAS CAS WE A0A10 BA I/O1I/O16 LDQM, UDQM VCC VSS VCCQ VSSQ NC
V54C316162V Rev. 2.9 September 2001
2
V54C316162V
DQMi
Column Decoder
Column Decoder
Sense Amplifier
RAS CAS WE DQMi
Timing Register
Row Decoder
Row Decoder
Row Address Buffer Column Address Counter Latency 8 Burst Length CLK Programming Register A0-A10, BA Column Address Buffer Row Addresses
Address
A0-A7, BA Column Addresses
V54C316162V-02
V54C316162V Rev.2.9 September 2001
3
Output Buffer
CLK CKE CS
Memor y Array Bank 0 512k x 16
Sense Amplifier
UDQM LDQM Memor y Array Bank 1 512k x 16
Input Buffer
CILETIV LESOM
Block Diagram
Write Control Logic MUX
I/O1-I/O16
Refresh Counter
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