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Details, datasheet, quote on part number:V54C316802VA
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Datasheet text preview:
MOSEL VITELIC
V54C316802VA HIGH PERFORMANCE 3.3 VOLT 2M X 8 SYNCHRONOUS DRAM 2 BANKS X 1MBit X 8
PRELIMINARY
CAS Latency = 3 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3)
8 125 MHz 8 ns 7 ns
10 100 MHz 10 ns 8 ns
12 83 MHz 12 ns 9 ns
Features
s 2 banks x 1Mbit x 8 organization s High speed data transfer rates up to 125 MHz s Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge s Single Pulsed RAS Interface s Dual Data Mask for Byte Control s Dual Banks controlled by A11 s Programmable CAS Latency: 1, 2, 3 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and full page for Sequential Type 1, 2, 4, 8 for Interleave Type s Multiple Burst Read with Single Write Operation s Automatic and Controlled Precharge Command s Random Column Address every CLK (1-N Rule) s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 44 Pin 400 mil TSOP-II s LVTTL Interface s Single +3.3 V ±0.3 V Power Supply
Description
The V54C316802VA is a dual bank Synchronous DRAM organized as 2 banks x 1Mbit x 8. The V54C316802VA achieves high speed data transfer rates up to 125 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating Temperature Range
0°C to 70 °C
Package Outline T
·
Access Time (ns) 8
·
Power 12
·
10
·
Std.
·
Temperature Mark
Blank
V54C316802VA Rev. 1.0 January 1998
1
MOSEL VITELIC
V 54
MOSEL-VITELIC MANUFACTURED SYCHRONOUS DRAM FAMILY C = CMOS PROCESS 3.3V, LVTTL, INTERFACE DEVICE PKG NUMBER REVISION LEVEL
V54C316802VA
C 31 68 02 T
SPEED PWR. 8 ns 10 ns 12 ns BLANK (NORMAL) T = TSOP-II 2 BANKS x 1MBit x 8 (4K REFRESH)
31168002-01
Description TSOP-II
Pkg. T
Pin Count 44
44 Pin Plastic TSOP-II PIN CONFIGURATION Top View
VCC I/O1 VSSQ I/O2 VCCQ I/O3 VSSQ I/O4 VCCQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
31161600 02
Pin Names
CLK CKE Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.3V) Ground Power for I/O's (+3.3V) Ground for I/O's Not connected
VSS I/O8 VSSQ I/O7 VCCQ I/O6 VSSQ I/O5 VCCQ NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS
CS RAS CAS WE A0A10 A11 (BS) I/O1I/O8 DQM, LDQM, UDQM VCC VSS VCCQ VSSQ NC
V54C316802VA Rev. 1.0 January 1998
2
MOSEL VITELIC
Absolute Maximum Ratings*
Ambient Temperature Under Bias .. 10 °C to +80 °C Storage Temperature (plastic) ......... -55 to +125 °C Input/Output Voltage... -0.5 to Min (VCC+0.5, 4.6) V Voltage Relative to VSS ......... -1.0V to +4.6 V Data Output Current .... 50 mA Power dissipation ......... 1.0 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V54C316802VA
Capacitance*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Symbol Parameter CI1 CI2 CIO Input Capacitance (A0 to A11) Input Capacitance RAS, CAS, WE, CS, CLK, CKE, DQM Output Capacitance (I/O)
Max. Unit
4 4 pF pF
5
pF
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
Row Decoder
Row Decoder
2048
2048 x 512 Memory Bank A
CKE
CKE Buffer Self Refresh Clock
1024
512
Row Address Counter Bank A Row/Column Select
8 Sense Amplifiers
Sense Amplifiers
Column Decoder and DQ Gate
CLK
CLK Buffer
Column Decoder and I/O Gate
8 8 8
11
Predecode A
3
8 Data Latches
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS)
Address Buffers (12)
12
Sequential Control Bank A
Data Latches
8
8 12 11
Mode Register
8
CS
CS Buffer
3
Sequential Control Bank B
8
Data Latches
11
Predecode B
8
RAS
Command Decoder
RAS Buffer
Bank B Row/Column Select
8
Column Decoder and I/O Gate Sense Amplifiers
WE
WE Buffer
Row Decoder
Row Decoder
2048
Memory Bank B 2048 x 512
DQM
DQM Buffer
V54C316802VA Rev. 1.0 January 1998
3
512
CAS
CAS Buffer
8
Data Input/Output Buffers
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
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