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Details, datasheet, quote on part number:V54C3256804V
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Datasheet text preview:
MOSEL VITELIC
V54C3256804V HIGH PERFORMANCE 3.3 VOLT 32M X 8 SYNCHRONOUS DRAM 4 BANKS X 8Mbit X 8
PRELIMINARY
-75 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Cycle Time (tCK2) Clock Access Time (tAC2) CAS Latency = 2 133MHz 7.5 ns 5.4 ns 10 ns 6 ns
-8PC 125MHz 8 ns 6 ns 10 ns 6 ns
-8 125MHz 8 ns 6 ns 12 ns 6 ns
Features
s 4 banks x 8Mbit x 8 organization s High speed data transfer rates up to 133 MHz s Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge s Single Pulsed RAS Interface s Data Mask for Read/Write Control s Four Banks controlled by BA0 & BA1 s Programmable CAS Latency: 2, 3 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and full page for Sequential Type 1, 2, 4, 8 for Interleave Type s Multiple Burst Read with Single Write Operation s Automatic and Controlled Precharge Command s Random Column Address every CLK (1-N Rule) s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 8192 cycles/64 ms s Available in 54 Pin 400 mil TSOP-II s LVTTL Interface s Single +3.3 V ±0.3 V Power Supply s -75 parts for PC133 3-3-3 operation s -8PC parts for PC100 2-2-2 operation s -8 parts for PC100 3-2-2 operation
Description
The V54C3256804V is a four bank Synchronous DRAM organized as 4 banks x 8Mbit x 8. The V54C3256804V achieves high speed data transfer rates up to 133 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating Temperature Range
0°C to 70°C
Package Outline T
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Access Time (ns) -75
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Power -8
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-8PC
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Std.
·
L
·
Temperature Mark
Blank
V54C3256804V Rev. 1.1 January 2000
1
MOSEL VITELIC
Description TSOP-II Pkg. T Pin Count 54
V54C3256804V
54 Pin Plastic TSOP-II PIN CONFIGURATION Top View
VCC I/O1 VCCQ NC I/O2 VSSQ NC I/O3 VCCQ NC I/O4 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
356804V-01
Pin Names
CLK CKE Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.3V) Ground Power for I/O's (+3.3V) Ground for I/O's Not connected
VSS I/O8 VSSQ NC I/O7 VCCQ NC I/O6 VSSQ NC I/O5 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
CS RAS CAS WE A0A12 BA0, BA1 I/O1I/O8 DQM VCC VSS VCCQ VSSQ NC
V54C3256804V Rev. 1.1 January 2000
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MOSEL VITELIC
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Symbol Parameter CI1 CI2 CIO CCLK Input Capacitance (A0 to A11) Input Capacitance RAS, CAS, WE, CS, CLK, CKE, DQM Output Capacitance (I/O) Input Capacitance (CLK)
V54C3256804V
Capacitance*
Max. Unit
5 5 pF pF
6.5 4
pF pF
*Note:Capacitance is sampled and not 100% tested.
Block Diagram
Column Addresses A0 - A9, AP, BA0, BA1 Row Addresses A0 - A12, BA0, BA1
Column address counter
Column address buffer
Row address buffer
Refresh Counter
Row decoder Memor y array
Column decoder Sense amplifier & I(O) bus
Row decoder Memor y array
Column decoder Sense amplifier & I(O) bus
Row decoder Memor y array Bank 2
Row decoder Memor y array Bank 3
Bank 0
Bank 1
8192 x 1024 x 8 bit
8192 x 1024 x 8 bit
Column decoder Sense amplifier & I(O) bus
8192 x 1024 x 8 bit
Column decoder Sense amplifier & I(O) bus
8192 x 1024 x 8 bit
Input buffer
Output buffer
Control logic & timing generator
I/O1-I/O8 CKE RAS CAS WE CS DQM CLK
V54C3256804V Rev. 1.1 January 2000
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