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Details, datasheet, quote on part number:V54C3256804VBS
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Datasheet text preview:
V54C3256(16/80/40)4V(T/S/B) 256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
PRELIMINARY
CILETIV LESO M
6 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Access Time (tAC2) CAS Latency = 2 166 MHz 6 ns 5.4 ns 5.4 ns
7PC 143 MHz 7 ns 5.4 ns 5.4 ns
7 143 MHz 7 ns 5.4 ns 6 ns
8PC 125 MHz 8 ns 6 ns 6 ns
Features
4 banks x 4Mbit x 16 organization 4 banks x 8Mbit x 8 organization 4 banks x16Mbit x 4 organization High speed data transfer rates up to 166 MHz Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge Single Pulsed RAS Interface Data Mask for Read/Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 for Sequential Type 1, 2, 4, 8 for Interleave Type Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Random Column Address every CLK (1-N Rule) Power Down Mode Auto Refresh and Self Refresh Refresh Interval: 8192 cycles/64 ms Available in 54 Pin TSOP II, 60 Ball WBGA and SOC BGA LVTTL Interface Single +3.3 V ±0.3 V Power Supply
Description
The V54C3256(16/80/40)4V(T/S/B) is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4. The V54C3256(16/80/40)4V(T/S/B) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Device Usage Chart
O perating Temperature Range
0°C to 70°C
Package Outline T/S/B
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Access Time (ns) 6
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P o we r 8 PC
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7PC
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7
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St d.
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L
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Temperature M ark
B lank
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
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V54C3256(16/80/40)4V(T/S/B)
CILETIV LESO M
256Mbit SDRAM Part Numbers
P a r t Number V54C3256164VAT V54C3256804VAT V54C3256404VAT V54C3256164VBT V54C3256804VBT V54C3256404VBT V54C3256164VAB V54C3256804VAB V54C3256404VAB V54C3256164VBS V54C3256804VBS V54C3256404VBS
Configuration 16M x 16 32M x 8 64M x 4 16M x 16 32M x 8 64M x 4 16M x 16 32M x 8 64M x 4 16M x 16 32M x 8 64M x 4
Process 0.17um 0.17um 0.17um 0.14um 0.14um 0.14um 0.17um 0.17um 0.17um 0.14um 0.14um 0.14um
Package TSOP TSOP TSOP TSOP TSOP TSOP WBGA WBGA WBGA SOC BGA SOC BGA SOC BGA
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
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V54C3256(16/80/40)4V(T/S/B)
CILETIV LESOM
Mosel Vitelic Manufactured S YNCHRONOUS DRAM FAMILY
V 54 C 3 25616 4 V A L T
Device Number S pecial F eature Speed 6 ns 7 ns 8 ns TSOP Component Package L=Low Power 4 Banks V=LVTTL Component Rev Level A=0.17um B=0.14um
Description TSOP-II
Pkg. T
Pin Count 54
C=CMOS Family 3.3V, LVTTL INTERFACE 16Mx16(8K Refresh)
54 Pin Plastic TSOP-II PIN CONFIGURATION Top View
VCC I/O1 VCCQ I/O2 I/O3 VSSQ I/O4 I/O5 VCCQ I/O6 I/O7 VSSQ I/O8 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
356164V-01
Pin Names
CLK CKE Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.3V) Ground Power for I/O's (+3.3V) Ground for I/O's Not connected
VSS I/O16 VSSQ I/O15 I/O14 VCCQ I/O13 I/O12 VSSQ I/O11 I/O10 VCCQ I/O9 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
CS RAS CAS WE A0A12 BA0, BA1 I/O1I/O16 LDQM, UDQM VCC VSS VCC Q VSSQ NC
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
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