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Details, datasheet, quote on part number:V54C3256804VCB7
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Datasheet text preview:
V54C3256(16/80/40)4V(T/C) 256Mbit SDRAM 3.3 VOLT, TSOP II / TRUECSP PACKAGE 16M X 16, 32M X 8, 64M X 4
PRELIMINARY
s s s s s s
CILETIV LESOM
System Frequency (fCK) Clock Cycle Time (tCK3)
6 166 MHz 6 ns 5.4 ns 5.4 ns
7P C 143 MHz 7 ns 5.4 ns 5.4 ns
7 143 MHz 7 ns 5.4 ns 6 ns
8PC 125 MHz 8 ns 6 ns 6 ns
Clock Access Time (tAC3) CA S Latency = 3 Clock Access Time (tAC2) CAS Latency = 2
Features
s s s s s 4 banks x 4Mbit x 16 organization 4 banks x 8Mbit x 8 organization 4 banks x16Mbit x 4 organization High speed data transfer rates up to 166 MHz Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge Single Pulsed RAS Interface Data Mask for R ead/Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 3 Programmable W rap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 for Sequential Type 1, 2, 4, 8 for Interleave Type Multiple Burst R ead with Single Write Operation Automatic and C ontrolled Precharge C ommand Random Column Address every CLK (1-N Rule) Power Dow n Mode Auto Refresh and Self Refresh Refresh Interval: 8192 cycles/64 ms Available in 60 Ball TrueCSP and 54 Pin TSOP II LVTTL Interface Single +3.3 V ±0.3 V Power Supply
Description
The V54C3256(16/80/40)4V(T/C) is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4. The V54C3256(16/80/40)4V(T/C) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device.
s s s s s s s s s
Device Usage Chart
O perating Temperature Range
0°C to 70°C
Package Outline T/ C
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Access Time (ns) 6
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P o we r 8PC
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7PC
·
7
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St d.
·
L
·
Temperature M ark
B lank
V54C3256(16/80/40)4V(T/C) Rev. 1.0 September 2001
1
V54C3256(16/80/40)4V(T/C) V 54 C 3 256XX 4 V A L C
Mosel Viteli c Manufactured SYNCHRONOUS DRAM FAMILY Device Number Speci al Feature Speed 6 ns 7 ns 8 ns Component Package L=Low Power 4 Banks Component Rev Level V=LVTTL
Description TrueCSP
A B C D E F G H J K L M N P R
DQ15 DQ14 VDDQ DQ11 DQ10 VDDQ NC NC VREF NC A12 A11 A8 A6 A4
CILETIV LESOM
Pkg. C Pin Count 60
C=CMOS Family 3.3V, LVTTL INTERF ACE 256Mb(8K Refresh)
60 Pin WB GA PIN CONFIGURATION Top View
256 Mb SDRAM Ball Assignment X16 X8 X4
(60-Ball TrueCSP)
X4
X8
X16
1
2
VSS VSSQ DQ13 DQ12 VSSQ DQ9 DQ8 VSS DQMH CLK CKE A9 A7 A5 VSS
1
DQ7 NC VDDQ DQ5 NC VDDQ NC NC VREF NC A12 A11 A8 A6 A4
2
VSS VSSQ DQ6 NC VSSQ DQ4 NC VSS DQM CLK CKE A9 A7 A5 VSS
1
NC NC VDDQ NC NC VDDQ NC NC VREF NC A12 A11 A8 A6 A4
2
VSS VSSQ DQ3 NC VSSQ DQ2 NC VSS DQM CLK CKE A9 A7 A5 VSS
1
VDD VDDQ DQ0 NC VDDQ DQ1 NC VDD WE# RAS# NC BA1 A0 A2 VDD
2
NC NC VSSQ NC NC VSSQ NC NC CAS# NC CS# BA0 A10 A1 A3
1
VDD VDDQ DQ1 NC VDDQ DQ3 NC VDD WE# RAS# NC BA1 A0 A2 VDD
2
DQ0 NC VSSQ DQ2 NC VSSQ NC NC CAS# NC CS# BA0 A10 A1 A3
1
VDD VDDQ DQ2 DQ3 VDDQ DQ6 DQ7 VDD WE# RAS# NC BA1 A0 A2 VDD
2
DQ0 DQ1 VSSQ DQ4 DQ5 VSSQ NC DQML CAS# NC CS# BA0 A10 A1 A3
A B C D E F G H J K L M N P R
TOP VIEW
V54C3256(16/80/40)4V(T/C) Rev. 1.0 September 2001
2
CILETIV LESOM
Mosel Vi telic Manufactured S YNCHRONOUS DRAM FAMILY Device Number
V54C3256(16/80/40)4V(T/C)
V 54 C 3 25616 4 V A L T
S pecial F eature Speed 6 ns 7 ns 8 ns Component Package L=Low Power 4 Banks Component Rev Level V=LVTTL
Description TSOP-II
Pkg. T
Pin Count 54
C=CMOS Family 3.3V, LVTTL INTERFACE 16Mx16(8K Refresh)
54 Pin Plastic TSOP-II PIN CONFIGURATION Top View
VCC I/O1 VCCQ I/O2 I/O3 VSSQ I/O4 I/O5 VCCQ I/O6 I/O7 VSSQ I/O8 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
356164V-01
Pin Names
CLK CKE Clock Input Clock Enable Chip Select Row A ddress Strobe Column A ddress Strobe Write E nable A ddress Inputs B ank Select Data Input/Output Data Mask P ower (+3.3V) Ground P ower for I/O's (+3.3V) Ground for I/O's Not connected
VSS I/O16 VSSQ I/O15 I/O14 VCCQ I/O13 I/O12 VSSQ I/O11 I/O10 VCCQ I/O9 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
CS RAS CAS WE A0A12 BA0, B A1 I/O1I/O16 LDQM, UDQM VCC VSS VCC Q VSSQ NC
V54C3256(16/80/40)4V(T/C) Rev. 1.0 September 2001
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