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Details, datasheet, quote on part number:V62C2162048LL55
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Datasheet text preview:
V62C2162048L(L)
Ultra Low Power 128K x 16 CMOS SRAM
Features
ˇ Low-power consumption - Active: 65mA ICC at 35ns - Stand-by: 10 ľA (CMOS input/output) 2 ľA (CMOS input/output, L version) ˇ 35/45/55/70/85/100 ns access time ˇ Equal access and cycle time ˇ Single +2.2V to 2.7V Power Supply ˇ Tri-state output ˇ Automatic power-down when deselected ˇ Multiple center power and ground pins for improved noise immunity ˇ Individual byte controls for both Read and Write cycles ˇ Available in 44 pin TSOP II / 48-fpBGA
Functional Description
The V62C2162048L is a Low Power CMOS Static RAM organized as 131,072 words by 16 bits. Easy memory expansion is provided by an active LOW (CE) and (OE) pin. This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the upper bits I/O9 - I/O16. Writing to these devices is performed by taking Chip Enable (CE) with Write Enable (WE) and Byte Enable (BLE/BHE) LOW. Reading from the device is performed by taking Chip Enable (CE) with Output Enable (OE) and Byte Enable (BLE/BHE) LOW while Write Enable (WE) is held HIGH.
Logic Block Diagram
Pre-Charge Circuit
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Data Cont Data Cont Vcc Vss
TSOPII / 48-fpBGA
Memory Array 1024 X 2048
I/O1 - I/O8 I/O9 - I/O16
I/O Circuit Column Select
A10 A11 A12 A13 A14 A15 A16
WE OE
BHE BLE CE
A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
Row Select
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REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
MOSEL VITELIC V62C2162048L(L)B
1 2 3 4 5 6 1 BLE I/O9 I/O10 VSS VCC I/O15 I/O16 NC 2 OE BHE I/O11 I/O12 I/O13 I/O14 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O2 I/O4 I/O5 I/O6 WE A11 6 NC I/O1 I/O3 VCC VSS I/O7 I/O8 NC
A B
C
D E
F G H
Note: NC means no Ball.
Top View
Top View
48 Ball - 9x12 fpBGA (Ultra Low Power)
C A1
PACKAGE OUTLINE DWG.
SYMBOL A A1 b c
UNIT:MM 1.05 +0.15 0.25 +0.05 0.35 +.05 0.30(TYP) 12.00 +0.10 5.25 9.00 +0.10 3.75 0.75TYP 0.10
A
SIDE VIEW
aaa
D D1
D D1 E
6 e
E1 e
5
aaa
E1 A B C D E F G H
4
3
2
1
BOTTOM VIEW
b SOLDER BALL
2
REV. 1.3 OCT 2001 V62C2162048L(L)
E
V62C2162048L(L)
Absolute Maximum Ratings * Parameter
Voltage on Any Pin Relative to Gnd Power Dissipation Storage Temperature (Plastic) Temperature Under Bias
Symbol
Vt PT Tstg Tbias
Minimum
-0.5 - -55 -40
Maximum
+4.6 1.0 +150 +85
Unit
V W
0
C
0C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE BHE I/O1-I/O8 I/O9-I/O16 X X High-Z High-Z L H Data Out High-Z H L High-Z Data Out L L Data Out Data Out L L Data In Data In L H Data In High-Z H L High-Z Data In X X High-Z High-Z H H High-Z High-Z Power Standby Active Active Active Active Active Active Active Active Mode Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Output Disable Output Disable
* Key: X = Don't Care, L = Low, H = High
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**) Parameter
Supply Voltage
Symbol
VCC Gnd VIH VIL
Min
2.2 0.0 2.2 -0.5*
Typ
2.5 0.0 -
Max
2.7 0.0 VCC + 0.2 0.8
Unit
V V V V
Input Voltage
* VIL min = -1.0V for pulse width less than tRC/2. ** For Industrial Temperature
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REV. 1.3 OCT 2001 V62C2162048L(L)
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