|
Details, datasheet, quote on part number:V826516B04S
| |
Datasheet text preview:
V826516B04S 128 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 16M x 64
PRELIMINARY
CILETIV LESO M
Features
JEDEC 200 Pin DDR Unbuffered Small-Outline, Dual In-Line memory module (SODIMM); 16,777,216 x 64 bit organization. Utilizes High Performance 8M x 16 DDR SDRAM in TSOPII-66 Packages Single +2.5V (± 0.2V) Power Supply Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All Inputs, Outputs are SSTL-2 Compatible 4096 Refresh Cycles every 64 ms Serial Presence Detect (SPD) DDR SDRAM Performance
Component Used
tC K tAC Clock Frequency (max.) Clock Access Time CAS Latency = 2.5
Description
The V826516B04S memory module is organized 16,777,216 x 64 bits in a 200 pin memory module. The 16M x 64 memory module uses 8 Mosel-Vitelic 8M x 16 DDR SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
-7
143
-75
133
-8
125
Units
MH z
(PC2 66A) (PC2 66B) (PC20 0)
7
7.5
8
ns
M odule Speed
A1 B0 B1 PC1600 (100MHz @ CL2) PC2100B (133MHz @ CL2.5) PC2100A (133MHz @ CL2)
V826516B04S Rev. 1.3 March 2002
1
V826516B04S
CILETIV LESO M
Part Number Information
V
MOSEL VITELIC MANUFACTURED
8
2
65
16
B
0
4
S
X
T
G - XX
SPEED A1 (100MHZ@CL2) B0 (133MHZ@CL2.5) B1 (133MHZ@CL2) LEAD FINISH G = GOLD
DDRSDR AM 2. 5V WID TH DEPTH 200 PIN Unbuffered SODIMM X16 COMPONENT REFRESH RATE 4K STTL 4 BANKS
COMPONENT PACKAGE, T = TSOP COMPONENT REV LEVEL
V826516B04S Rev. 1.3 March 2002
2
V826516B04S
DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE
VDD/VDDQ
CILETIV LESO M
Block Diagram
S1 S0 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
BA0-BA1: DDR SDRAMs D0 - D7 A0-A13: DDR SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 Clock Input CK0/CK0 CK1/CK1 CK2/CK2 Clock Wiring SDRAMs 4 SDRAMs 4 SDRAMs NC CK CK Card Edge *Clock Net Wiring R=120 ± 5%
S
D0
LDQS S LDM I/0 0 I/0 1 I/0 2 D4 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
DQS4 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS5 DM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS6 DM6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS7 DM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
S
D2
LDQS S LDM I/0 0 I/0 1 I/0 2 D6 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
S
D1
LDQS S LDM I/0 0 I/0 1 I/0 2 D5 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
S
D3
LDQS S LDM I/0 0 I/0 1 I/0 2 D7 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
Dram1 Dram2 Dram3 Dram4
VDDSPD
SPD D0 - D7 D0 - D7 SCL WP
Serial PD SDA A0 SA0 A1 SA1 A2 SA2
VREF VSS V DDID
D0 - D7 D0 - D7 Strap: see Note 4
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ.
V826516B04S Rev. 1.3 March 2002
3
|
|
