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Part: V826516G04S
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> 128 MB
Description: 128 MB 200-PIN DDR Unbuffered Sodimm 2.5 Volt 16M X 64, 200 Pin Sodimm
Company: Mosel-Vitelic
Datasheet: Download V826516G04S datasheet File size : 85 kB
Request For quote: Find where to buy V826516G04S
Datasheet text preview:
V826516G04S 128 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 16M x 64
PRELIMINARY
CILETIV LESO M
Features
JEDEC 200 Pin DDR Unbuffered Small-Outline, Dual In-Line memory module (SODIMM); 16,777,216 x 64 bit organization. Utilizes High Performance 16M x 8 DDR SDRAM in TSOPII-66 Packages Single +2.5V (± 0.2V) Power Supply Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All Inputs, Outputs are SSTL-2 Compatible 4096 Refresh Cycles every 64 ms Serial Presence Detect (SPD) DDR SDRAM Performance
Component Used
tC K tAC Clock Frequency (max.) Clock Access Time CAS Latency = 2.5
Description
The V826516G04S memory module is organized 16,777,216 x 64 bits in a 200 pin memory module. The 16M x 64 memory module uses 8 Mosel-Vitelic 16M x 8 DDR SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
-7
143
-75
133
-8
125
Units
MH z
(PC2 66A) (PC2 66B) (PC20 0)
7
7.5
8
ns
M odule Speed
A1 B0 B1 PC1600 (100MHz @ CL2) PC2100B (133MHz @ CL2.5) PC2100A (133MHz @ CL2)
V826516G04S Rev. 1.5 March 2002
1
V826516G04S
CILETIV LESO M
Part Number Information
V
MOSEL VITELIC MANUFACTURED
8
2
65
16
G
0
4
S
X
T
G - XX
SPEED A1 (100MHZ@CL2) B0 (133MHZ@CL2.5) B1 (133MHZ@CL2) LEAD FINISH G = GOLD
DDRSDR AM 2. 5V WID TH DEPTH 200 PIN Unbuffered SODIMM X8 COMPONENT REFRESH RATE 4K STTL 4 BANKS
COMPONENT PACKAGE, T = TSOP COMPONENT REV LEVEL
V826516G04S Rev. 1.5 March 2002
2
V826516G04S
CILETIV LESO M
Block Diagram
CS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S
D0
D4
DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D1
DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D5
DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D2
DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
Clock Wiring Clock Input CK0/CK0 CK1/CK1 CK2/CK2
D6
SDRAMs 4 SDRAMs 4 SDRAMs NC
Serial PD SCL WP SDA A0 SA0 A1 SA1 A2 SA2
DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D3
DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D7
Dram1
±
R=120 5%
Dram2 Dram3 Dram4
Card Edge *Clock Net Wiring
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE
BA0-BA1: DDR SDRAMs D0 - D7
VDDSPD
SPD D0 - D7 D0 - D7
A0-A13: DDR SDRAMs D0 - D7 VDD/VDDQ RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 VREF V SS VDDID
D0 - D7 D0 - D7 Strap: see Note 4
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ.
V826516G04S Rev. 1.5 March 2002
3
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V8-1
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