Details, datasheet, quote on part number: 68HC12BE32MSE1
CompanyMotorola Semiconductor Products
DatasheetDownload 68HC12BE32MSE1 datasheet


Features, Applications


DESCRIPTION: ATD status bits and conversion counter are not reset properly when writing any ATD register while an active A/D conversion sequence is in the process of completion. WORKAROUND: When starting a new sequence, perform two writes to control registers 4/5 in quick secession. If the first write occurs when the status bit/conversion counter is not reset, the second write will correct ATD operation.

DESCRIPTION: The (VRH-VRL)/2 internal reference conversion result may or $81. WORKAROUND: If the (VRH-VRL)/2 internal reference is used (perhaps for system diagnostics), expected pass result may or $81.

DESCRIPTION: To transmit a message using the BDLC, the user writes the first byte of the message to be transmitted into the BDLC data register (BDR). This will initiate the transmission process at the beginning of the next idle bus state.An invalid symbol being received by the BDLC clears any byte that had been previously written to the BDR. This will inhibit the transmission process until the user writes another byte to the BDR. The following scenario describes an event sequence that would prevent the user from knowing that an invalid symbol was received and that the BDR had been cleared. WORKAROUND: A two level strategy has been developed that positively signals the need to restart the transmission of a message. The first level looks for the special case of reception of an illegal symbol with a byte pending transmission in the BDLC data register, as described above. The second level uses a transmit watchdog timer to spot any case of a transmission not occurring within a maximum amount If an illegal symbol interrupt occurs with a byte pending transmission in the BDR, reload the BDR with the first byte of that message to restart transmission.

DESCRIPTION: CRC error in received message does not prevent IFR transmission. WORKAROUND: In response to the CRC Error interrupt ($18 in BSVR), immediately write an $FF byte into the BDR, and then clear the lower four bits in BCR2 (TSIFR, TMIFR0, TMIFR1, TEOD). This will cancel the IFR transmission.

DESCRIPTION: When programmed to transmit a single byte Type 2 IFR (byte loaded in the BDR and TSIFR bit set in BCR2), the BDLC will attempt to transmit a single IFR byte following the EOD of the message currently being received. If the byte to be transmitted loses arbitration, the BDLC will continue to retry transmission until it is successful or an error occurs or the TEOD bit is set. WORKAROUND: (Short form) When the first RXIFR interrupt occurs the requester message has been received without errors (invalid symbol or CRC). When the BDLC receives back correctly the IFR byte is was trying to transmit, then response by this node is complete and the requester message received can be passed to the application layer. Ignore any invalid symbol error that occurs after the first RXIFR interrupt, since transmission of IFRs are not retried.

DESCRIPTION: Breakpoint Address and Data registers are properly reset only upon Power on Reset. WORKAROUND: To insure BRKAH, BRKAL, BRKDH and BRKDL registers have the correct default values, always clear each immediately after reset.

DESCRIPTION: If the REV or REVW instructions are interrupted while processing a rules list, the results from the instructions may be incorrect. The Condition Code Register and Index Register Y (weight pointer for REVW) may be incorrect when the stacking occurs for the interrupt. The REV and


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