|Company||Motorola Semiconductor Products|
|Datasheet||Download 68HC912BC32MSE1 datasheet
This errata provides mask-set specific information applicable to the following MC68HC912BC32 MCU mask set devices: 3J15G
The mask set is identified by a four-character code consisting of a letter, two numerical digits, and a letter, for example F74B. Slight variations to the mask set identification code may result in an optional numerical digit preceding the standard four-character code, for example 0F74B.
Device markings indicate the week of manufacture and the mask set used. The data is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. The date code "9115" would indicate the 15th week of the year 1991.
Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC, or ZC prefix denotes special/custom device. An XC prefix denotes device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC prefix.
When contacting a Motorola representative for assistance, please have the MCU device mask set and date code information available.Specifications and information herein are subject to change without notice.
FLASH: FASTER WAIT MODE WAKEUP RECOVERY TIME FOR FLASH AR457
Flash requires 250nsec delay for wakeup from wait mode with FEESWAI=1. If the operating bus frequency is greater than 4MHz, the Flash cannot be used when recovering from WAIT mode when the FEESWAI bit is equal to `1'.If your interrupt vectors are located in the Flash array, do not set the FEESWAI bit in Wait mode.
If the (VRHVRL)/2 internal reference is used (perhaps for system diagnostics), expected pass result may or $81.BKP: ADDRESS AND DATA REGISTERS RESET ONLY ON POR
Breakpoint Address and Data registers are properly reset only upon Power on Reset.
To ensure BRKAH, BRKAL, BRKDH and BRKDL registers have the correct default values, always clear each immediately after reset.INT: EDGE SENSITIVE IRQ DOES NOT WORK CORRECTLY DURING STOP AR528
When using an edge sensitive IRQ signal to trigger an interrupt service routine and the IRQ is not released during servicing, the part will not enter stop mode if the following executed instruction is STOP.When IRQ is set to be edge sensitive, release pin before executing STOP instruction.
INT: WAIT CANNOT BE EXITED IF XIRQ/IRQ LEVEL DEASSERTION OCCURS WITHIN PARTICULAR WINDOW OF TIME AR600
The device can get trapped in WAIT mode if, on exiting the WAIT instruction, the deassertion timing of the XIRQ or level-sensitive IRQ occurs within a particular timeframe. Only reset will allow recovery. Noise/bounce on the pins could also cause this problem.
1. Use edge-triggered IRQ (IRQE=1) instead of XIRQ or level-triggered IRQ. 2. Use RTI , timer interrupts, KWU or other interrupts (except level-sensitive IRQ or XIRQ) to exit WAIT. If using RTI, it must be enabled in WAIT (RSWAI=0) and the COP must be disabled (CME=0). 3. Assert XIRQ or level-sensitive IRQ until the interrupt subroutine is entered. 4. Add de-bouncing logic to prevent inadvertent highs when exiting WAIT.INTERRUPTS: ARE NOT MASKED DURING 1ST CYCLE OF ANY BACKGROUND INSTRUCTION
There is a cycle at the beginning of executing a BDM instruction (tag, trace, instruction) that is susceptible to being interrupted directly after the background has executed. Since the interrupt source is masked, the interrupt vector that is requested is $FFF6. The BDM firmware at $FFF6 points to the routine at $FF24. The interrupt was stacked when it was taken, but the BDM routines do not un-stack (no RTI). When you return from BDM, the stack pointer is pointing to the wrong place.
This problem may occur when using the BDM. Avoid using TRACE command during cycles where interrupts become unmasked (i.e. TRACE of a CLI if interrupts are pending). Do not use the BGND instruction directly following an instruction that clears the or I mask bits. Do not try to TAG the opcode directly following an instruction that clears the or I mask bits if interrupts are pending. There is still the scenario where an interrupt occurs exactly during the execution of the 1st cycle of any BDM execution, which will still cause the problem.
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